脉冲同步电路（慢时钟域到快时钟域）

module代码

`timescale 1ns / 1ps
module pulse_sync_02(
			input clk1,			//快时钟
			input clk2,			//慢时钟
			input rst_n,
			input pulse_in,		
			output pulse_out);
			
			wire toggle_pulse;
			reg pulse_01;
			reg pulse_buf_1,pulse_buf_2;
			
			assign toggle_pulse = (pulse_in)? (~pulse_01):pulse_01;
			
			always @ (posedge clk1 or negedge rst_n)
				begin
					if (!rst_n)
						pulse_01 <= 1'b0;
					else	
						pulse_01 <= toggle_pulse;						
				end
			
			always @ (posedge clk2 or negedge rst_n)
				begin
					if (!rst_n)
						begin
							pulse_buf_1 <= 1'b0;
							pulse_buf_2 <= 1'b0;
						end	
					else
						begin
							pulse_buf_1 <= toggle_pulse;
							pulse_buf_2 <= pulse_buf_1;
						end
				end
			
				assign pulse_out = pulse_buf_2 ^ pulse_buf_1;
endmodule

测试代码

`timescale 1ns / 1ps


module sim_pulse_sync_02;

        reg clk1;
        reg clk2;
        reg rst_n;
        reg pulse_in;
        wire pulse_out;
        
pulse_sync_02 m0(
			.clk1(clk1),			
			.clk2(clk2),			
			.rst_n(rst_n),
			.pulse_in(pulse_in),		
			.pulse_out(pulse_out));
			
		initial
		  begin
		      clk1 = 1'b0;
		      clk2 = 1'b0;
		      rst_n = 1'b1;
		      pulse_in = 1'b0;
		      #20 rst_n = 1'b0;
		      #40 rst_n = 1'b1;
		      #10 pulse_in = 1'b1;
		      #20 pulse_in = 1'b0;
		      #80 pulse_in = 1'b1;
		      #20 pulse_in = 1'b0;
		  end
		  
		  always #10 clk1 = ~clk1;
		  always #20 clk2 = ~clk2;
endmodule

仿真结果
生成RTL结构