Round Robin 总线轮询仲裁器 verilog代码 testbench功能仿真

Roy_wang_24

已于 2022-02-24 20:14:14 修改

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分类专栏：数字芯片文章标签： verilog fpga 芯片

于 2020-08-29 21:11:46 首次发布

本文链接：https://blog.csdn.net/qq_35579390/article/details/108299509

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根据上次一总线分配的情况结合当前的输入请求分配总线

verilog代码

module round_robin_bus_arbiter(
			input clk,
			input rst_n,
			input [2:0] req, //假如需要给3个主机分配总线
			output reg [1:0] grant_out //2'b00 A获得总线， 2‘b01 B获得总线 , 2'10 c获得总线
			);
			
			
			always @ (posedge clk or negedge rst_n)
				begin
					if (!rst_n)
						grant_out <= 1'b11;
					else
						case(grant_out)
							2'b00: //之前A获得总线
								case (req)
									3'b000:	grant_out <= 2'b00;
									3'b001:	grant_out <= 2'b00;
									3'b010: grant_out <= 2'b01;
									3'b011:	grant_out <= 2'b01;
									3'b100:	grant_out <= 2'b10;
									3'b101: grant_out <= 2'b10;
									3'b110: grant_out <= 2'b01;
									3'b111: grant_out <= 2'b01;
									default: grant_out <= 2'b00;
								endcase
							2'b01: //之前B获得总线
								case (req)
									3'b000:	grant_out <= 2'b01;
									3'b001:	grant_out <= 2'b00;
									3'b010: grant_out <= 2'b01;
									3'b011:	grant_out <= 2'b00;
									3'b100:	grant_out <= 2'b10;
									3'b101: grant_out <= 2'b10;
									3'b110: grant_out <= 2'b01;
									3'b111: grant_out <= 2'b01;
									default: grant_out <= 2'b01;
								endcase
							2'b10: //之前C获得总线
								case (req)
									3'b000:	grant_out <= 2'b10;
									3'b001:	grant_out <= 2'b00;
									3'b010: grant_out <= 2'b01;
									3'b011:	grant_out <= 2'b00;
									3'b100:	grant_out <= 2'b10;
									3'b101: grant_out <= 2'b00;
									3'b110: grant_out <= 2'b01;
									3'b111: grant_out <= 2'b00;
									default: grant_out <= 2'b10;
								endcase
							default: grant_out <= 2'b00;
						endcase
								
				end	
endmodule

testbench

`timescale 1ns / 1ps



module sim_test_001;
        
        reg clk;
        reg rst_n;
        reg [2:0] req;
        wire [1:0] grant_out;
        
		  test_001 mo( 
		          .clk(clk),
			      .rst_n(rst_n),
			      .req(req), 
			      .grant_out(grant_out)
			);
			
			always #10 clk = ~clk;
			
			initial 
			     begin
			         clk = 1'b0;
			         rst_n = 1'b1;
			         req = 3'b000;
			         #20  rst_n = 1'b0;
			         #20  rst_n = 1'b1;
			         #20 req = 3'b001;
			         #20 req = 3'b010;
			         #20 req = 3'b011;
			         #20 req = 3'b100;
			         #20 req = 3'b101;
			         #20 req = 3'b110;
			         #20 req = 3'b111;
			         
			     end
		  
endmodule