自己创建axi-lite总线,
给led rgbled输出接口
需要4+3*2=10个reg,作为输出
具体IP核内部
增加pwm.v
`define DELAY_BITS 6
// 1 - wire DAC
module pwm(
input clk,
input [7:0] pwm_val ,
output reg pwm_pin
);
reg [`DELAY_BITS+7:0] runner =0 ;
always @ (posedge clk) runner <= runner+1 ;
always @ (posedge clk) pwm_pin <= runner[7+`DELAY_BITS:`DELAY_BITS] < pwm_val ;
endmodule
例化,
reg因为pwm细粒度是256,reg只用了8bits
pwm LED0( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg0[7:0] ) , .pwm_pin( LED[0] ) );
pwm LED1( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg1[7:0] ) , .pwm_pin( LED[1] ) );
pwm LED2( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg2[7:0] ) , .pwm_pin( LED[2] ) );
pwm LED3( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg3[7:0] ) , .pwm_pin( LED[3] ) );
pwm LEDrgb1_r( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg4[7:0] ) , .pwm_pin( LED_rgb[0] ) );
pwm LEDrgb1_g( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg5[7:0] ) , .pwm_pin( LED_rgb[1] ) );
pwm LEDrgb1_b( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg6[7:0] ) , .pwm_pin( LED_rgb[2] ) );
pwm LEDrgb2_r( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg7[7:0] ) , .pwm_pin( LED_rgb[3] ) );
pwm LEDrgb2_g( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg8[7:0] ) , .pwm_pin( LED_rgb[4] ) );
pwm LEDrgb2_b( .clk( S_AXI_ACLK ) , .pwm_val( slv_reg9[7:0] ) , .pwm_pin( LED_rgb[5] ) );
输出bitstream
sdk
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "sleep.h"
void set_led_pwn( unsigned int a ,unsigned int b ){
*(volatile unsigned int * )(0x43c00000 + (4*a)) = b ;
// Xil_Out32 ( (0x43c00000 + (4*a) ) ,b ) ;
}
int main()
{
unsigned char i ;
unsigned char start_value=0 ;
for(;;)
{
for(i=0;i<4;++i) set_led_pwn( i , start_value ) ;
set_led_pwn( 4 , start_value) ;
set_led_pwn( 5 , 0) ;
set_led_pwn( 6 , 0) ;
for(i=6;i<9;++i) set_led_pwn( i , start_value-i*32 ) ;
usleep(200*1000);
start_value += 32 ;
}
}