输出vga 5个时序要求线,RGB H V_sync
根据my_vga_syn 输出的行列序号,用一个dsp计算地址,送给vga_dpram ,读取地址对应的值,然后转换为RGB;也可以通过
module vga_control(
input pixcel_clk ,
input sys_clk ,//wr
input rst_n ,
input[18:0] din ,
input feed_data ,//en,使能
input feed_addr ,
//out
output[4-1:0] R,
output[4-1:0] G,
output[4-1:0] B,
output v_synch,
output h_synch
);
//中间信号定义
reg[18:0] buffer_feed;
always @(posedge sys_clk)
if(feed_addr) buffer_feed <= din;
else if(feed_data) buffer_feed <= 1 + buffer_feed ;//
wire[10:0] line_count,pixel_count;
wire dp_en;//,v_synch,h_synch
my_vga_syn ttu(
.pixel_clock(pixcel_clk ) ,
.rst_i(rst_n ) ,
.h_synch(h_synch ) ,
.v_synch( v_synch) ,
.dp_en(dp_en ) ,
.line_count (pixel_count ) ,
.pixel_count (pixel_count )
);
wire [18:0] pixel_addr ;
wire [11:0] buff_out ;
assign pixel_addr= line_count * 640 + pixel_count;
vga_dpram vga_ram(
. wr_clk(sys_clk ),
.wr_din(din[11:0]),
.wr_addr(buffer_feed),
. wr (feed_data ),
.rd_clk(pixcel_clk),
.rd_addr(pixel_addr) ,
.rd_dout(buff_out)
);
assign R=(dp_en)?buff_out[11:8]:0;
assign G=(dp_en)?buff_out[7:4]:0;
assign B=(dp_en)?buff_out[3:0]:0;
endmodule
top只输出5个信号,输入时钟复位,利用clk wrap IP核产生pixel clk,内部产生feed_data
module vga_top(
output h_synch,v_synch,
output [3:0] R,G,B,
input clk_i,rst_i
);
reg [40:0] cntr ;
design_1_wrapper design_1_i (
.clk_in1(clk_i),
.clk_out1(pixel_clock),
.locked( ),
.reset(1'b0)
);
always @(posedge pixel_clock) cntr <= cntr + 1 ;
vga_drv vga_drv (
.pixel_clock( pixel_clock ),
.h_synch(h_synch ),
.v_synch( v_synch ),
.R( R ),
.G( G ),
.B( B ),
.sys_clk( pixel_clock ),
.rst_i( rst_i ),
.feed_addr( 1'b0 ),
.feed_data( 1'b1 ),
.feed_data( 1'b0),
.din( cntr[ 21+11 :21] )
);
endmodule