FPGA边沿检测Verilog实现（包含上升沿，下降沿，双边沿）详细介绍

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边沿检测

脉冲边沿的特性：两侧电平发生了变化

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CODE

代码如下（示例）：

module edge_detect(input clk,
                   input rst_n, 
                   input data_in, 
                   output raising_edge_detect, 
                   output falling_edge_detect, 
                   output double_edge_detect);
reg data_in_d1;
reg data_in_d2;

always @ (posedge clk,negedge rst_n)
begin
    if(!rst_n)
    begin data_in_d1 <= 1'b0; data_in_d2 <= 1'b0; end 
    else
    begin data_in_d1 <= data_in; data_in_d2 <= data_in_d1;end 
end 
assign raising_edge_detect = data_in_d1  & (~data_in_d2);//上升沿
assign falling_edge_detect = ~data_in_d1 &  data_in_d2;//下降沿
assign double_edge_detect  = data_in_d1 ^ data_in_d2;//双边沿
endmodule

RTL

经过综合后的电路图如上图所示，可以根据上升，或者下降沿的信号变化来进行判断。