使用任意一种编程或脚本语言(C,Verilog,SystemVerilog,shell,perl,Python)实现32位十六进制转化为二进制数(如abcd0123->1010101111001101

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
void HextoTwo(int num)
{
    int res;
    int i = 0;
    char buf[BUFSIZ][5] = {"0000"};
    char reference[16][5] = {"0000","0001","0010","0011",\
                        "0100","0101","0110","0111",\
                        "1000","1001","1010","1011",\
                        "1100","1101","1110","1111"};

    while(num / 16 !=  0)
    {
        res = num % 16;
        strcpy(buf[i++], reference[res]);
        num = num / 16;
    }

    res = num % 16;
    strcpy(buf[i++], reference[res]);

    while(i > 0)
        printf("%s ", buf[--i]);
}
//采用递归
void HextoTwo(int num)
{
    int remainder;
    char buf[16][5] = {"0000","0001","0010","0011",\
                        "0100","0101","0110","0111",\
                        "1000","1001","1010","1011",\
                        "1100","1101","1110","1111"};
    if(0 == num)
        return;

    remainder = num % 16;
    HextoTwo(num >> 4);
    printf("%s ", buf[remainder]);
}

int main()
{
    int num = 0xfa;
    HextoTwo(num);
    return EXIT_SUCCESS;
}

iscas2spice spice netlist generation tool -- version 2.2 by Jingye Xu @ VLSI Group, Dept. of ECE, UIC, June, 2008 This tool reads the ISCAS85 benchmark circuit "*.bench" file and translate the file into SPICE netlist using the given technology and the standard cell library. platform: linux x86 sytem Input: ISCAS85 benchmark circuit: *.bench; standard cell library: stdcells.sclb; standard cell models: stdcells.lib; interconnect paramaters: *.int; Output: SPICE netlist: out.sp The whole procedure of the tools can be divided into several steps: 1. Gate replacement: replace the gates that can't be found in the with the gates in the standard cell lib. (break.pl) Output: *.bench, *.bench.bak 2. Generate the GSRC files: generate the GSRC files for the fengshui placer. (gsrcgen.pl) Output: gsrcfile/iscas.* 3. Placement: using the fengshui placement tool to perform the component placement. (fs50) Output: gsrcfile/iscas_fs50.pl 4. Generate ISPD file: tanslate the placement results into ISPD98 format file that can be used as the input of the global router. (gsrc2ispd.pl) Output: gsrcfile/iscas.laby.txt 5. Perform the routing: use the labyrinth global router to perform the routing. (mazeRoute) Output: gsrcfile/output 6. Generate the SPICE netlist: use all the available information to generate the final SPICE netlist. (spicegen.pl) Output: out.sp Usage: iscas2spice.pl Iscas85BenchmarkFile [-C/L/N] options: -C :default value, use the RC model for interconnect -L :use the RLC model for interconnect -N :treat interconnect as short circuit wire This package used the fengshui placement tools and labyrinth global routing tools, for information regarding these two free tools, please vist: http://www.ece.ucsb.edu/~kastner/labyrinth/ http://vlsicad.cs.binghamton.edu/software.html For information regarding this software itself please visit: http://wave.ece.uic.edu/~iscas2spice Many thanks to my advisor Masud H. Chowdhury for his support!
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