DDR4 IP核的配置与控制

DDR4 IP核的配置与控制

IP配置如下图

顶层外接引脚

	input  wire         pll_ref_clk,         //  pll_ref_clk.clk,               PLL reference clock input
	input  wire         oct_rzqin,           //  oct.oct_rzqin,         Calibrated On-Chip Termination (OCT) RZQ input pin
	output wire [0:0]   mem_ck,              //  mem.mem_ck,            CK clock
	output wire [0:0]   mem_ck_n,            // .mem_ck_n,          CK clock (negative leg)
	output wire [16:0]  mem_a,               // .mem_a,             Address
	output wire [0:0]   mem_act_n,           // .mem_act_n,         Activation command
	output wire [1:0]   mem_ba,              // .mem_ba,            Bank address
	output wire [0:0]   mem_bg,              // .mem_bg,            Bank group
	output wire [0:0]   mem_cke,             // .mem_cke,           Clock enable
	output wire [0:0]   mem_cs_n,            // .mem_cs_n,          Chip select
	output wire [0:0]   mem_odt,             // .mem_odt,           On-die termination
	output wire [0:0]   mem_reset_n,         // .mem_reset_n,       Asynchronous reset
	output wire [0:0]   mem_par,