有限状态机
Moore型
状态机的输出仅与当前状态值有关, 且只在时钟边沿到来时才会有状态变化。
Mealy型:
状态机的输出不仅与当前状态值有关, 而且与当前输入值有关。
两者的区别:
Mealy比Moore输出提前一个周期,同时可节省一个状态
举个栗子:
0101序列检测,可循环
Moore型
module fsm_moore (
input wire clk,
input wire reset_n,
input wire data_in,
output reg out
);
reg [4:0] state,next_state;
parameter SIDLE=5'b00001,S1=5'b00010,S2=5'b00100,S3=5'b01000,S4=5'b10000;
//FF
always@(posedge clk or negedge reset_n)
if(!reset_n)
state<=SIDLE;
else
state<=next_state;
//transiton
always@(*)begin
case (state)
SIDLE:
if(data_in==0)
next_state=S1;
else
next_state=SIDLE;
S1:
if(data_in==1)
next_state=S2;
else
next_state=S1;
S2:
if(data_in==0)
next_state=S3;
else
next_state=SIDLE;
S3:
if(data_in==1)
next_state=S4;
else
next_state=S1;
S4:
if(data_in==0)
next_state=S3;
else
next_state=SIDLE;
default :next_state=SIDLE;
endcase
end
//oupout
always @(posedge clk or negedge reset_n) begin
if(!reset_n)
out<=1'b0;
else if(state==S4)
out<=1'b1;
else
out<=1'b0;
end
endmodule //fsm_moore
仿真:
mealy型:
module fsm_mealy (
input wire clk,
input wire reset_n,
input wire data_in,
output reg out
);
reg [3:0]state,next_state ;
parameter S0=4'b0001,S1=4'b0010,S2=4'b0100,S3=4'b1000;
//FF
always @(posedge clk or negedge reset_n) begin
if(!reset_n)
state<=S0;
else
state<=next_state;
end
//transition
always @(*) begin
case(state)
S0:
if(data_in==0)
next_state=S1;
else
next_state=S0;
S1:
if(data_in==1)
next_state=S2;
else
next_state=S1;
S2:
if(data_in==0)
next_state=S3;
else
next_state=S0;
S3:
if(data_in==1)
next_state=S1;
else
next_state=S0;
default:next_state=S0;
endcase
end
//output
always @(posedge clk or negedge reset_n) begin
if(!reset_n)
out<=1'b0;
else if(state ==S3 && data_in ==1) //注意输出条件
out<=1'b1;
else
out<=1'b0;
end
endmodule //fsm_mealy
仿真: