VerilogA——计数器

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已于 2022-06-24 14:14:19 修改

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分类专栏：模拟IC设计文章标签：数模混合 VerilogA 循环计数器 HDL 硬件建模

于 2022-06-24 14:12:48 首次发布

本文链接：https://blog.csdn.net/qq_41019681/article/details/125444319

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带有低电平有效复位的 8-bit 循环计数器VerilogA代码

// VerilogA for COUNTER_8B, veriloga

`include "constants.vams"
`include "disciplines.vams"

module COUNTER_8B (B7, B6, B5, B4, B3, B2, B1, B0, CLK, RSTN);
	electrical     B7, B6, B5, B4, B3, B2, B1, B0, CLK, RSTN;
	parameter real trise = 1p;
	parameter real tfall = 1p;
	parameter real tdely = 0;
	parameter real vlogic_high = 1;
	parameter real vlogic_low  = 0;
	parameter real vtrans_clk  = 0.5;
	`define num_bits  8
	real i;
	real t;
	real halfscal;
	real fun[0:`num_bits-1];
	integer m;

	analog begin
	  @ (initial_step) begin
	   	i=0;
		halfscal = 128;
	  end
  
	  @ (cross(V(CLK) - vtrans_clk, +1) or cross(V(RSTN) - vtrans_clk, -1)) begin

		if(V(RSTN) < vtrans_clk) begin
			i = 0;
		end 
		else if (i == 255) begin
	    		i = 0;
	   	end
		else 
		begin
	    		i=i+1;
	   	end
	
		t = i;

		for (m=(`num_bits-1); m >=0; m=m-1) begin
			fun[m] = 0;
	  		if (t > halfscal-1) begin
	   			fun[m]=vlogic_high;
	   			t = t - halfscal;
	   		end
			else begin
	   			fun[m]=vlogic_low;
	   		end
	   		t = t * 2;
	  	end
	  end


	V(B7) <+ transition( fun[7], tdely, trise, tfall );
	V(B6) <+ transition( fun[6], tdely, trise, tfall );
	V(B5) <+ transition( fun[5], tdely, trise, tfall );
	V(B4) <+ transition( fun[4], tdely, trise, tfall );
	V(B3) <+ transition( fun[3], tdely, trise, tfall );
	V(B2) <+ transition( fun[2], tdely, trise, tfall );
	V(B1) <+ transition( fun[1], tdely, trise, tfall );
	V(B0) <+ transition( fun[0], tdely, trise, tfall );

	`undef num_bits

	end
 
endmodule