FPGA实验六——计数器、ROM和DDS

计数器、ROM和DDS

实验要求1：

• 用计数器生成地址、读取ROM数据
• 用SignalTap观察ROM的输出波形
• 理解二进制补码和无符号数
• 修改技术增量值，观察波形变化，实考输出频率和计数器增量值的关系

①Verilog HDL代码

带增量输入的计数器模块

module cnt_incr(
  CLK   ,   // clock
  INCR  ,   // counter increase value 
  CNTVAL);  // counter value
input CLK;
input  [7-1:0] INCR;
output [7-1:0] CNTVAL;

reg [7-1:0] CNTVAL;

always @ (posedge CLK) begin
  CNTVAL <= INCR + CNTVAL;
end
endmodule   // module cnt_incr

ROM代码

module sine_rom(
  CLK    ,           // clock
  RA     ,           // read address
  RD     );          // read data
input          CLK;
input  [6  :0] RA;
output [7  :0] RD;
reg    [7  :0] RD;
always @ (posedge CLK)
  case(RA)
     7 'd 0     :RD = #1 8 'b 00000000; //      0 0x0 
     7 'd 1     :RD = #1 8 'b 00000110; //      6 0x6 
     7 'd 2     :RD = #1 8 'b 00001100; //     12 0xC 
     7 'd 3     :RD = #1 8 'b 00010010; //     18 0x12 
     7 'd 4     :RD = #1 8 'b 00011000; //     24 0x18 
     7 'd 5     :RD = #1 8 'b 00011110; //     30 0x1E 
     7 'd 6     :RD = #1 8 'b 00100100; //     36 0x24 
     7 'd 7     :RD = #1 8 'b 00101010; //     42 0x2A 
     7 'd 8     :RD = #1 8 'b 00110000; //     48 0x30 
     7 'd 9     :RD = #1 8 'b 00110110; //     54 0x36 
     7 'd 10    :RD = #1 8 'b 00111011; //     59 0x3B 
     7 'd 11    :RD = #1 8 'b 01000001; //     65 0x41 
     7 'd 12    :RD = #1 8 'b 01000110; //     70 0x46 
     7 'd 13    :RD = #1 8 'b 01001011; //     75 0x4B 
     7 'd 14    :RD = #1 8 'b 01010000; //     80 0x50 
     7 'd 15    :RD = #1 8 'b 01010101; //     85 0x55 
     7 'd 16    :RD = #1 8 'b 01011001; //     89 0x59 
     7 'd 17    :RD = #1 8 'b 01011110; //     94 0x5E 
     7 'd 18    :RD = #1 8 'b 01100010; //     98 0x62 
     7 'd 19    :RD = #1 8 'b 01100110; //    102 0x66 
     7 'd 20    :RD = #1 8 'b 01101001; //    105 0x69 
     7 'd 21    :RD = #1 8 'b 01101100; //    108 0x6C 
     7 'd 22    :RD = #1 8 'b 01110000; //    112 0x70 
     7 'd 23    :RD = #1 8 'b 01110010; //    114 0x72 
     7 'd 24    :RD = #1 8 'b 01110101; //    117 0x75 
     7 'd 25    :RD = #1 8 'b 01110111; //    119 0x77 
     7 'd 26    :RD = #1 8 'b 01111001; //    121 0x79 
     7 'd 27    :RD = #1 8 'b 01111011; //    123 0x7B 
     7 'd 28    :RD = #1 8 'b 01111100; //    124 0x7C 
     7 'd 29    :RD = #1 8 'b 01111101; //    125 0x7D 
     7 'd 30    :RD = #1 8 'b 01111110; //    126 0x7E 
     7 'd 31    :RD = #1 8 'b 01111110; //    126 0x7E 
     7 'd 32    :RD = #1 8 'b 01111111; //    127 0x7F 
     7 'd 33    :RD = #1 8 'b 01111110; //    126 0x7E 
     7 'd 34    :RD = #1 8 'b 01111110; //