数字IC笔试题|verilog实现CRC-8的串行计算

题目如下：
verilog实现：

`timescale 1ns / 1ps
//
module crc(clk,rst_n,data,data_valid,crc_start,crc_out,crc_valid,crc_out_parallel);
input clk,rst_n;
input data;  //串行输入数据
input data_valid; //串行数据有效标识；
input crc_start;

output wire crc_out;
output reg [7:0] crc_out_parallel;
 
output reg crc_valid;

parameter idle = 3'b001;
parameter crc_cal = 3'b010;
parameter crc_output = 3'b100;
parameter polynomial = 8'b0000_0111;

reg [2:0] current_state,next_state;

always@(posedge clk or negedge rst_n)
begin 
if(rst_n==1'b0)
  
	  current_state<=idle;
else 
      current_state<=next_state;
end 

reg [5:0] cnt_in;
reg [2:0] cnt_out;
 
always@(*)
begin 
        case(current_state)
	        idle :    
			       if(crc_start==1'b1)
				        next_state = crc_cal;
				   else 
				        next_state = idle;
		    crc_cal:
			       if(cnt_in==6'd32)
				        next_state = crc_output;
				   else 
				        next_state = crc_cal;
			crc_out:
			       if(cnt_out==3'd7)
				        next_state = idle;
				   else 
				        next_state = crc_output;
		endcase
end 

always@(posedge clk or negedge rst_n)  //计数输入
begin 
if(rst_n==1'b0)
    cnt_in<=6'd0;
else if(current_state