IP-ROM

IP-ROM

1. 概述

• 只读存储器

2. 配置
3. 应用

verilog_to_ROM.v

module Verilog_to_ROM
(
	CLK_50M,RST_N,readdate,address
);

input CLK_50M;
input RST_N;
input [4:0] address;
output[7:0] readdate;
memory	memory_inst (
	.address ( address ),
	.clock ( CLK_50M ),
	.q ( readdate )
	);

endmodule

verilog_to_ROM.vt

`timescale 1 ps/ 1 ps
module Verilog_to_ROM_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg CLK_50M;
reg RST_N;
reg [4:0] address;
reg [4:0] address_n;
// wires                                               
wire [7:0]  readdate;

// assign statements (if any)                          
Verilog_to_ROM i1 (
// port map - connection between master ports and signals/registers   
	.CLK_50M(CLK_50M),
	.RST_N(RST_N),
	.address(address),
	.readdate(readdate)
);
initial                                                
begin                                                  
	CLK_50M=0;
	RST_N=0;
	#10 RST_N=1;
	#1000000 $stop;
end   
always #10000 CLK_50M=~CLK_50M;                                                 
always@ (negedge CLK_50M or negedge RST_N)                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
	if(!RST_N)
		address<=1'b0;
	else
		address<=address_n;
end   
always@ (*)                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
	if(address==5'd31)
		address=1'b0;
	else
		address_n=address+1'b1;
end                                                   
endmodule

verilog_to_ROM.mif

signaltap 波形