IP-RAM
- 概述
- 随机存取存储器
- SRAM 和DRAM
- 配置
- 单端口
- 双端口
- 应用
verilog_to_RAM.v
module Verilog_to_RAM
(
CLK_50M,RST_N,address,wrdata,rddata,wren,rden,time_cnt
);
input CLK_50M;
input RST_N;
output reg[5:0] time_cnt;
output reg[4:0] address;
output reg[7:0] wrdata;
output [7:0] rddata;
output wren;
output rden;
reg [5:0] time_cnt_n;
reg [4:0] address_n;
reg [7:0] wrdata_n;
always@(posedge CLK_50M or negedge RST_N)
begin
if(!RST_N)
time_cnt<=1'b0;
else
time_cnt<=time_cnt_n;
end
always@(*)
begin
if(time_cnt==6'd63)
time_cnt_n=1'b0;
else
time_cnt_n=time_cnt+1'b1;
end
//
always@(negedge CLK_50M or negedge RST_N)
begin
if(!RST_N)
address<=1'b0;
else
address<=address_n;
end
always@(*)
begin
if(address==5'd31)
address_n=1'b0;
else
address_n=address+1'b1;
end
assign wren=(time_cnt >=1'b0&&time_cnt<=5'd31)? 1'b1:1'b0;
always@(negedge CLK_50M or negedge RST_N)
begin
if(!RST_N)
wrdata<=1'b0;
else
wrdata<=wrdata_n;
end
always@(*)
begin
if(time_cnt >=1'b0&&time_cnt<=5'd31)
wrdata_n=time_cnt;
else
wrdata_n=wrdata;
end
assign rden=(time_cnt >=6'd32&&time_cnt<=6'd63)? 1'b1:1'b0;
memory memory_inst (
.address ( address ),
.clock ( CLK_50M),
.data ( wrdata ),
.rden ( rden ),
.wren ( wren ),
.q ( rddata )
);
endmodule
verilog_to_RAM.vt
`timescale 1 ps/ 1 ps
module Verilog_to_RAM_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg CLK_50M;
reg RST_N;
// wires
wire [4:0] address;
wire [7:0] rddata;
wire rden;
wire [5:0] time_cnt;
wire [7:0] wrdata;
wire wren;
// assign statements (if any)
Verilog_to_RAM i1 (
// port map - connection between master ports and signals/registers
.CLK_50M(CLK_50M),
.RST_N(RST_N),
.address(address),
.rddata(rddata),
.rden(rden),
.time_cnt(time_cnt),
.wrdata(wrdata),
.wren(wren)
);
initial
begin
CLK_50M=1'b0;
RST_N=1'b0;
#10 RST_N=1'b1;
#1000000 $stop;
end
always #1000 CLK_50M=~CLK_50M;
endmodule
modelsim图
signaltap 图
图片有一点时序错误不想改了
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