Edgedetect

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] temp;
    
    initial temp = 16'd0;
    
    always@(posedge clk)
        temp <= in;
    always@(posedge clk)
        pedge <= in & ~temp[7:0];//仅检测上升沿

endmodule

检测上升沿要将上一状态取反后再与当前状态相与

检测上升沿和下降沿，上一状态和当前状态相异或