这一题想了好久一开始看这波形图捋不清,其实就是检测输入信号的所有跳变(0到1,1到0)。
需要一个寄存器state保存状态值;
波形图的变化如下
in | (存储上一in状态)state | (对比前两者)anyedge |
0000 (初始态) | 0000 (初始态) | 0000 (初始态) |
0010(2) | (posedge clk)0000 | 0010(2) |
0010(2) | (posedge clk)0010 | 0000 |
1110(e) | (posedge clk)0010 | 1100(c) |
1110(e) | (posedge clk)1110 | 0000 |
0000 | (posedge clk)1110 | 1110(e) |
0010 | (posedge clk)0000 | 0010(2) |
0010 | (posedge clk)0010 | 0000 |
虽然只是简单的异或,捋清楚波形变化还是稍微花了点时间。
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] state ;
always @(posedge clk)
begin
state <= in;
anyedge <= state^in;
end
endmodule
刷题刷题继续刷题。