HDLBits练习——Edgedetect2

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

---

前言

两个输入，包括一个时钟clk，一个输入信号in；一个输出边缘检测信号anyedge。

代码

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] in_old;
    always@(posedge clk)begin
        in_old<=in;
        anyedge<=in^in_old;
    end    
endmodule

总结

对于边缘检测，其代码为in^in_old，分为in&~in_old（上升沿检测）和 !in&in_old（下降沿检测）两种。