【HDLBits刷题】Edgedetect2.

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

 

Module Declaration

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

在一个8bit的变量中，从一个周期到另一个周期期间，检测输入信号变化。即上升沿变化或下降沿变化。输出应在0变为1后产生。

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0]zhongjian = 8'h00;
    always@(posedge clk)
        begin
            zhongjian <= in;
            anyedge <= in^zhongjian;
        end

本题需要大家来检测信号上升沿或下降沿的变化。在上一个问题中我们是用 & 来检测信号的上升沿，但在本题总可以采取 xor 的形式来检测。