移位寄存器实现序列检测-Verilog

//移位寄存器实现10010检测
module Detect_10010(
	input clk,
	input rst_n,
	input data_in,
	output reg [4:0] data_out, //这里使用reg类型的原因是在always块中使用了非阻塞赋值
	output flag
    );

always @ (posedge clk or negedge rst_n)
begin
	if(!rst_n)
		data_out <= 5'd0;
	else
		data_out <= ({data_out[3:0],data_in});
end

assign flag = (data_out == 5'b10010) ? 1'b1 : 1'b0;

endmodule

//仿真代码
module sim_Detect_10010();

reg clk;
reg rst_n;
reg data_in;
wire [4:0] data_out;  //仿真的时候输出是wire类型，不可以使用reg类型
wire flag;

Detect_10010 u1(
	.clk (clk),
	.rst_n (rst_n),
	.data_in (data_in),
	.data_out (data_out),
	.flag (flag)
);

initial 
begin
	clk = 0;
	rst_n =0;
	data_in = 0;
	#30;
	data_in = 1;
	#20
	data_in = 0;
	#20
	data_in = 0;
	#20
	data_in = 1;
	#20
	data_in = 0;
end

always #10 clk = ~ clk;

endmodule