2021-10-23

Verilog Language

Modules:Hierarchy

Modules and vectors

Module shift8

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside. (See also: mux9to1v)

这个练习是module_shift的扩展。而不是模块端口只是单引脚，我们现在有模块与矢量作为端口，你将附加线矢量，而不是普通的电线。与Verilog中的其他地方一样，端口的矢量长度不必与连接到它的线匹配，但这将导致矢量的零填充或构造。本练习不使用向量长度不匹配的连接。
有一个模块my_dff8，它有两个输入和一个输出(它实现了一组8d触发器)。实例化其中的三个，然后将它们连接在一起，使长度为3的8位宽移位寄存器。另外，创建一个4对1的多路复用器(未提供)，根据sel[1:0]选择输出内容:输入d处的值，第一个、第二个或第三个d触发器之后的值。(本质上，sel选择输入延迟多少周期，从0到3个时钟周期。)
提供给你的模块是:模块my_dff8(输入clk，输入[7:0]d，输出[7:0]q);
不提供多路复用器。一种可能的方法是在always块中使用case语句。(参见:mux9to1v)

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] a;
    wire [7:0] b;
    wire [7:0] c;
    my_dff8 my_dff8_inst1(clk,d,a);
    my_dff8 my_dff8_inst2(clk,a,b);
    my_dff8 my_dff8_inst3(clk,b,c);
    always@(*)
        begin 
            case(sel)
                2'b00:q = d;
                2'b01:q = a;
                2'b10:q = b;
                2'b11:q = c; 
            endcase
        end
endmodule

\\官方答案
module top_module (
	input clk,
	input [7:0] d,
	input [1:0] sel,
	output reg [7:0] q
);

	wire [7:0] o1, o2, o3;		// output of each my_dff8
	
	// Instantiate three my_dff8s
	my_dff8 d1 ( clk, d, o1 );
	my_dff8 d2 ( clk, o1, o2 );
	my_dff8 d3 ( clk, o2, o3 );

	// This is one way to make a 4-to-1 multiplexer
	always @(*)		// Combinational always block
		case(sel)
			2'h0: q = d;
			2'h1: q = o1;
			2'h2: q = o2;
			2'h3: q = o3;
		endcase

endmodule