目录
顺序执行模块
定义输入为clk,输出为q,a;则:
module serial1(clk,a,q);
input clk;
output a,q;
reg a,q;
always @(posedge clk)
begin
q = ~q;
a = ~q;
end
endmodule
module serial2(clk,a,q);
input clk;
output a,q;
reg a,q;
always @(posedge clk)
begin
a = ~q;
q = ~q;
end
endmodule
并行执行模块
定义输入为clk;输出为a,q;则:
module paral1(clk,a,q);
input clk;
output a,q;
reg a,q;
always @(posedge clk)
begin
q = ~q;
end
always @(posedge clk)
begin
a = ~q;
end
endmodule
module paral2(clk,a,q);
input clk;
output a,q;
reg a,q;
always @(posedge clk)
begin
a = ~q;
end
always @(posedge clk)
begin
q = ~q;
end
endmodule