牛客Verilog刷题

8

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
genvar i;
generate
	for(i=0;i<8;i=i+1)begin
		assign data_out[i]=data_in[7-i];
	end
endgenerate
endmodule

75

`timescale 1ns/1ns

module lcm#(
parameter DATA_W = 8)
(
input [DATA_W-1:0] A,
input [DATA_W-1:0] B,
input 			vld_in,
input			rst_n,
input 			clk,
output	wire	[DATA_W*2-1:0] 	lcm_out,
output	wire 	[DATA_W-1:0]	mcd_out,
output	reg					vld_out
);
reg [DATA_W-1:0] A0,B0;
reg [DATA_W*2-1:0] lcm_out_temp;
reg flag;
always@(posedge clk,negedge rst_n)begin
    if(~rst_n)begin
        A0<='d0;
        B0<='d0;
        lcm_out_temp<='d0;
        vld_out<='d0;
        flag<='d0;
    end
    else begin
        if(vld_in)begin
            {A0,B0}<=A>B?{A,B}:{B,A};
            lcm_out_temp<=A*B; 
            flag<='d1; 
        end
        else begin
            A0<=flag ? ((A0>B0)?A0-B0:B0):'d0;
            B0<=flag ? ((A0>B0)?B0:A0):'d0; 
          // B0<=flag ? ((A0>B0)?B0:A0-B0):'d0; 
            lcm_out_temp<=lcm_out_temp;
            flag=vld_out?'d0:flag;
        end      
        vld_out<=flag && (A0==B0);
    end
end
assign mcd_out=vld_out?A0:'d0;
//assign lcm_out=vld_out?lcm_out_temp/A0:'d0;
assign lcm_out=lcm_out_temp/mcd_out;


endmodule

module lcm#(
parameter DATA_W = 8)
(
input [DATA_W-1:0] A,
input [DATA_W-1:0] B,
input 			vld_in,
input			rst_n,
input 			clk,
output	wire	[DATA_W*2-1:0] 	lcm_out,
output	wire 	[DATA_W-1:0]	mcd_out,
output	reg					vld_out
);
reg [DATA_W-1:0]A0,B0;
reg [DATA_W*2-1:0] lcm_out_temp;
reg flag;
always@(posedge clk,negedge rst_n)begin
	if(!rst_n)begin
		A0<='d0;
		B0<='d0;
		flag<='d0;
		lcm_out_temp<='d0;
		vld_out<='d0;
	end
	else if(vld_in)begin
		A0<=A;
		B0<=B;
		flag<='d1;
		lcm_out_temp<=A*B;
		vld_out<='d0;
	end
	else if(flag)begin
		A0<=(A0>B0)?A0-B0:B0;
		B0<=(A0>B0)?B0:A0;
		flag<=(A0==B0)?'d0:'d1;
		lcm_out_temp<=lcm_out_temp;
		vld_out<= A0==B0;
	end
	else begin
		A0<=A0;
		B0<=B0;
		flag<=flag;
		lcm_out_temp<=lcm_out_temp;
		vld_out<='d0;
	end
end

assign  mcd_out=(A0==B0 && flag)?A0:mcd_out;
assign lcm_out=lcm_out_temp/mcd_out;

endmodule