HDLBits刷题--testbench

module top_module();
	reg   clk;
	initial begin
		clk = 1'd0;
	end
	dut dut_1( clk);
	always #5 clk = ~clk;
endmodule

module top_module ( output reg A, output reg B );//
    // generate input patterns here
    initial begin
		A<=1'b0;
        B<=1'b0;
        #10
        A<=1'b1;
        #5
        B<=1'b1;
        #5
        A<=1'b0;   
        #20
        B<=1'b0;        
    end
endmodule

module top_module();
    reg [1:0] in;
    wire out;
    initial begin
       in<=2'd0;
        #10
        in<=2'd1;
        #10
        in<=2'd2;
        #10
        in<=2'd3;
    end
    andgate andgate_inst(
        .in(in),
        .out(out));
endmodule

module top_module();
reg clk;
    reg in;
    reg [2:0] s;
    wire out;
    
    initial begin
       clk<=1'd0; 
        in<=1'd0;
        s<=3'd2;
        #10
        s<=3'd6;
        #10
        in<=1'd1;
        s<=3'd2;
        #10
        in<=1'd0;
        s<=3'd7;
        #10
        in<=1'd1;
        s<=3'd0;
        #30
        in<=1'd0;
        
    end
    
    q7 q7_inst(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out));
    always #5 clk=~clk;
endmodule

module top_module ();
reg clk;
    reg reset;
    reg t;
    wire q;
    
    initial begin
       clk<=1'd0;

        reset<=1'd1;
        t<=1'd0;
        #10
               reset<=1'd0;
        t<=1'd1;
    end
    tff tff_inst(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q));
    
    always #1 clk=~clk;
endmodule

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
    reg [9:0] counter;
    
    always @(posedge clk )begin
        if(load)begin
            counter<=data;
        end    
        else begin
            if(counter==10'd0)
            counter<=10'd0; 
            else 
            counter<=counter-10'd1; 
        end
       
    end
    assign tc=(counter==10'd0)? 1'd1:1'd0;

endmodule