HDLbits刷题笔记——FSM

最新推荐文章于 2024-09-30 13:22:45 发布

victor-f

最新推荐文章于 2024-09-30 13:22:45 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_45579489/article/details/126920663

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该文描述了使用Verilog语言设计的三种不同类型的状态机：FSM1实现了基于两个状态A和B的简单逻辑；FSM2是一个基于输入j和k的开关状态机，可以在OFF和ON之间切换；FSM3是一个使用独热码表示的四状态机，其状态转换依赖于输入in和当前状态。所有状态机都包含同步复位功能，并通过输出out反映当前状态。

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FSM1/FSM1s


module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output reg out);//  

    parameter A=1'b0, B=1'b1; 
    reg state, next_state;
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)
            state<=B;
        else
            state<=next_state;
    end
    
    always @(*) begin    // This is a combinational always block
        case(state)
            A:if(in)
                next_state<=A;
              else
                next_state<=B;
            B:if(in)
                next_state<=B;
              else
                next_state<=A;            
        endcase      
    end

    always @(posedge clk) begin    // This is a sequential always block
        if(state==B)
           out<=1'b1; 
        else
           out<=1'b0;             
    end
  //  assign out=(state==B)?1'b1:1'b0;

endmodule

FSM2/FSM2s

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=1'b0, ON=1'b1; 
    reg state, next_state;
    
 	always @(posedge clk, posedge areset) begin
        if(areset)
            state<=OFF;
        else
            state<=next_state;
    end
    always @(*) begin
        case(state)
            OFF:if(j)
                	next_state<=ON;
            	else
                    next_state<=OFF;
                
            ON:if(k)
                	next_state<=OFF;
            	else
                    next_state<=ON;  
        endcase
    end
    // Output logic
    assign out = (state == ON)?1'b1:1'b0;
endmodule

FSM3/FSM3s

独热码

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    
    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;
    reg [3:0]state, next_state;   
 	always @(posedge clk, posedge areset)  begin
        if(areset)
            state<=4'd1;
        else
            state<=next_state;
    end
    assign next_state[A] =state[A]&(~in)|state[C]&(~in);
    assign next_state[B] =state[A]&in|state[B]&in|state[D]&in;
    assign next_state[C] =state[B]&(~in)|state[D]&(~in);
    assign next_state[D] =state[C]&in;
    // Output logic
    assign out=state[D];
endmodule