数码管显示译码的Verilog实现

数码管译码显示

要求：开关二进制，数码管显示十六进制数字

实现的Verilog代码：

module DigitalTube(
    input wire [3:0] high_data,
    input wire[3:0] low_data,
    input wire clk,
    output reg [6:0] led,
    output reg [3:0] en
    );

	reg [3:0] data;
	reg [15:0] times;

	initial times = 0;

	always @ (posedge clk)
		begin
		times = times + 16'b1;
		if(times == 40000)
			times = 16'b0;
		end

	always @ (posedge clk)
		begin
		if(times > 20000)
			begin
			en = 4'b1101;
			data = high_data;
			end
		else
			begin
			en = 4'b1110;
			data = low_data;
			end
		case(data)
			4'b0000: led = 7'b1000000;	//0
			4'b0001: led = 7'b1111001;	//1
			4'b0010: led = 7'b0100100;	//2
			4'b0011: led = 7'b0110000;	//3
			4'b0100: led = 7'b0011001;	//4
			4'b0101: led = 7'b0010010;	//5
			4'b0110: led = 7'b0000010;	//6
			4'b0111: led = 7'b1111000;	//7
			4'b1000: led = 7'b0000000;	//8
			4'b1001: led = 7'b0010000;	//9
			4'b1010: led = 7'b0001000;	//A
			4'b1011: led = 7'b0000011;	//b
			4'b1100: led = 7'b1000110;	//C
			4'b1101: led = 7'b0100001;	//d
			4'b1110: led = 7'b0000110;	//E
			4'b1111: led = 7'b0001110;	//F
	endcase
	end
endmodule

上述代码实现的是输入是8位二进制，输出两位十六进制数。添加管脚约束后，即可在FPGA上实现。