题Count clock

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

一个1-12的两位的BCD计数器与0-5的一位计数器

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss);
    wire ens,enm0,enm1,enh;
    decade s0(clk,reset,ena,ss[3:0]);
    assign ens=(ena&&ss[3:0]==9)?1'b1:1'b0;
    de6 s1(clk,reset,ens,ss[7:4]);
    assign enm0=(ena&&ss[3:0]==9&&ss[7:4]==5)?1'b1:1'b0;
    decade m0(clk,reset,enm0,mm[3:0]);
    assign enm1=(ena&&mm[3:0]==9&&ss[3:0]==9&&ss[7:4]==5)?1'b1:1'b0;
    de6 m1(clk,reset,enm1,mm[7:4]);
    assign enh=(ena&&mm[7:4]==5&&mm[3:0]==9&&ss[3:0]==9&&ss[7:4]==5)?1'b1:1'b0;
    de12 h(clk,reset,enh,hh[7:0]);
    
    always@(posedge clk)
       pm<=(hh[7:4]==1&&hh[3:0]==1&&mm[7:4]==5&&mm[3:0]==9&&ss[3:0]==9&&ss[7:4]==5&&~reset&&ena)?(~pm):(pm);
endmodule
module decade(input clk,
    input reset,
    input ena,
    output [3:0]q);
    always@(posedge clk)
        if(reset)
            q<=4'h0;
    else if(ena&&q==4'h9)
        q<=4'h0;
    else if(ena)
        q<=q+1;
endmodule
module de6(input clk,
    input reset,
    input ena,
    output [3:0]q);
    always@(posedge clk)
        if(reset)
            q<=4'h0;
    else if(ena&&q==4'h5)
        q<=4'h0;
    else if(ena)
        q<=q+1;
endmodule
module de12(input clk,
    input reset,
    input ena,
    output [7:0]q);
    always@(posedge clk)
        if(reset)
            q<=8'h12;
    else if(ena&&q==8'h12)
        q<=8'h1;
    else if(ena&&q==8'h9)
        q<=q+1+6;
    else if(ena)
        q<=q+1;
endmodule