FPGA学习实现奇分频、偶分频

FPGA学习实现奇分频、偶分频

设计目标：初始时钟信号为50Mhz，实现八分频和七分频

实现八分频

时序图

CLK_DIV8代码

module CLK_DIV8 (
    input wire clk,
    input wire rst_n,
    output reg clk_div8_out
);

reg [2:0]cnt;

//计数器
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        cnt <= 4'd0;
    end
    else begin
        cnt <= cnt + 4'd1;
    end
end

//八分频
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        clk_div8_out = 1'b0;
    end
    else if (cnt>=4 && cnt <=7) begin
        clk_div8_out = 1'b1;
    end
    else begin
        clk_div8_out = 1'b0;
    end
end


    
endmodule

tb文件

`timescale 1ns/1ps

module CLK_DIV8_tb ();
    
reg clk;
reg rst_n;
wire clk_div8_out;

initial begin
    clk = 1'd0;
    rst_n = 1'd0;
    #2
    rst_n = 1'd1;

end

always #10 clk = ~clk;
 
CLK_DIV8 CLK_DIV8_1(
    .clk(clk),
    .rst_n(rst_n),
    .clk_div8_out(clk_div8_out)
);

endmodule

仿真结果

实现七分频

时序图

如上图，通过在上升沿和下降沿拉起波形的或运算，来实现50%占空比的七分频。同样的，我们也可以通过控制flag1和flag2拉起的波形从而通过与、异或、同或运算来实现奇分频。

CLK_DIV7代码

module CLK_DIV7 (
    input wire clk,
    input wire rst_n,
    output wire clk_div7_out
);

reg [2:0]cnt;
reg clk_div7_flag1;
reg clk_div7_flag2;

//计数器
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        cnt <= 4'd0;
    end
    else if (cnt == 6) begin
        cnt <= 4'd0;
    end
    else begin
        cnt <= cnt + 4'd1;
    end
end

//clk_div7_flag1上升沿
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        clk_div7_flag1 = 1'b0;
    end
    else if (cnt>=3 && cnt <=5) begin
        clk_div7_flag1 = 1'b1;
    end
    else begin
        clk_div7_flag1 = 1'b0;
    end
end

//clk_div7_flag2下降沿
always @(negedge clk or negedge rst_n) begin
    if (~rst_n) begin
        clk_div7_flag2 = 1'b0;
    end
    else if (cnt>=3 && cnt <=5) begin
        clk_div7_flag2 = 1'b1;
    end
    else begin
        clk_div7_flag2 = 1'b0;
    end
end

//clk_div7_out七分频
assign clk_div7_out = clk_div7_flag1 | clk_div7_flag2;
    
endmodule

tb文件

`timescale 1ns/1ps

module CLK_DIV7_tb ();
    
reg clk;
reg rst_n;
wire clk_div7_out;

initial begin
    clk = 1'd0;
    rst_n = 1'd0;
    #2
    rst_n = 1'd1;

end

always #10 clk = ~clk;
 
CLK_DIV7 CLK_DIV7_1(
    .clk(clk),
    .rst_n(rst_n),
    .clk_div7_out(clk_div7_out)
);

endmodule

仿真结果