Verilog 刷题-Exams/review2015 fsm

 还有一种方法是通过计数器，我这里想简单一点就是把所有状态列出来了。sh4这个状态可以去掉。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    reg [5:0]next_state,state;
    parameter w = 0,s1=1,s2=2,s3=3,s4=4,sh1=5,sh2=6,sh3=7,sh4=8,countingg =9,donee= 10;
    always@(*)begin 
        case(state )
            w:next_state = data?s1:w;
            s1:next_state = data?s2:w;
            s2:next_state = data?s2:s3;
            s3:next_state = data?s4:w;
            s4:next_state = sh1;
            sh1:next_state = sh2;
            sh2:next_state = sh3;
            sh3:next_state = countingg;
            countingg:next_state = done_counting?donee:countingg;
            donee:next_state = ack?w:donee;
        endcase
    end
    always@(posedge clk)begin 
        if(reset)state <=w;
        else state <=next_state;
    end
    assign done = (state == donee);
    assign shift_ena = (state == sh1|state == sh2|state == sh3|state == s4);
    assign counting = (state == countingg );
endmodule