Verilog 刷题-Dff8

最新推荐文章于 2023-05-04 10:17:42 发布

Tuffy77

最新推荐文章于 2023-05-04 10:17:42 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_54421341/article/details/125200902

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实现8位D触发器

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    D d1(.clk(clk),.d(d[0]),.q(q[0]));
    D d2(.clk(clk),.d(d[1]),.q(q[1]));
    D d3(.clk(clk),.d(d[2]),.q(q[2]));
    D d4(.clk(clk),.d(d[3]),.q(q[3]));
    D d5(.clk(clk),.d(d[4]),.q(q[4]));
    D d6(.clk(clk),.d(d[5]),.q(q[5]));
    D d7(.clk(clk),.d(d[6]),.q(q[6]));
    D d8(.clk(clk),.d(d[7]),.q(q[7]));
   
endmodule
module D(input clk,d,output q);
    always@(posedge clk)
        q <= d;
endmodule

看了答案发现想的太复杂了

module top_module(
	input clk,
	input [7:0] d,
	output reg [7:0] q);
	
	// Because q is a vector, this creates multiple DFFs.
	always @(posedge clk)
		q <= d;
	
endmodule