Verilog 刷题-Lfsr5

 移位寄存器，按照图里的连接就好。

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    always@(posedge clk)begin
        if(reset)q<=5'h1;
        else begin
        q[4]<= q[0];
        q[3]<= q[4];
        q[2]<= q[3]^q[0];
        q[1]<= q[2];
            q[0]<= q[1];
        end
    end
endmodule