计组预备实验2：七段LED数码管显示译码器设计

module preexp2(load, clk, rst, in, out, sel);
input[15:0] in;
input load, clk, rst;//rst清零信号，load置数信号
output reg[7:0] out;
output reg[2:0] sel;
//output reg[2:0] select;
reg[15:0] counter;//计数
reg[3:0] data;
reg clk_alt;
reg[9:0] l;
always@(posedge clk)
begin
	if(l>=1023) l<=0;
	else l<=l+1;
	clk_alt<=l[2];
end
always@(posedge clk)
begin
	if(sel<3)sel<=sel+1;
	else sel<=0;
end


always@(sel)
begin
case(sel)
		0:data<=counter[3:0];
		1:data<=counter[7:4];
		2:data<=counter[11:8]; 
		3:data<=counter[15:12];
endcase
end
always@(posedge clk_alt, posedge rst)
begin
	if(rst==1)     counter<=0;
	else if(load==1)counter<=in;
	else counter<=counter+1;
end
always@(data)
	case(data)
		0:out=63;//0011 1111
		1:out=6;
		2:out=91;
		3:out=79;
		4:out=102;
		5:out=109;
		6:out=175;
		7:out=7;
		8:out=127;
		9:out=111;
		10:out=119;
		11:out=124;
		12:out=57;
		13:out=94;
		14:out=121;
		15:out=113;
	endcase
endmodule

（待补充）

注意：最后的译码是以十进制方式赋值的，为了直观起见，最好写成16进制或者二进制。