HDLBits从零开始——第101题到110题答案

最新推荐文章于 2024-07-20 17:11:37 发布

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最新推荐文章于 2024-07-20 17:11:37 发布

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分类专栏： HDLBits 文章标签： fpga开发经验分享学习

本文链接：https://blog.csdn.net/qq_62179548/article/details/129777110

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第101题：Decade counter again

第102题：Slow decade counter

第103题：Counter 1-12

第104题：Counter 1000

第105题：4-digit decimal counter

第106题：12-hour clock

第107题：4-bit shift register

第108题：Left/right rotator

第109题：Left/right arithmetic shift by 1 or 8

第110题：5-bit LFSR

第101题：Decade counter again

module top_module 
(
    input           clk     ,
    input           reset   ,
    output [3:0]    q
);

always@(posedge clk)
    if(reset)
        q <= 1;
    else if(q == 10)
        q <= 1;
    else    
        q <= q+1;

endmodule

第102题：Slow decade counter

module top_module 
(
    input           clk     ,
    input           slowena ,
    input           reset   ,
    output [3:0]    q
);

always@(posedge clk)
    if(reset)
        q <= 0;
    else if((q == 9)&&(slowena == 1'b1))
        q <= 0;
    else if(slowena)
        q <= q+1;

endmodule

第103题：Counter 1-12

module top_module 
(
    input           clk     ,
    input           reset   ,
    input           enable  ,
    output [3:0]    Q       ,
    output          c_enable,
    output          c_load  ,
    output [3:0]    c_d
);
        
assign  c_enable = enable;
assign  c_load = (Q == 12 && enable == 1) || reset?1:0;
assign  c_d = 4'd1;

count4 the_counter (clk, c_enable, c_load, c_d, Q);

endmodule

第104题：Counter 1000

module top_module 
(
    input           clk     ,
    input           reset   ,
    output          OneHertz,
    output [2:0]    c_enable
);

wire    [3:0]   q1;
wire    [3:0]   q2;
wire    [3:0]   q3;

assign  c_enable[0] = 1'b1;
assign  c_enable[1] = (q1 == 9);
assign  c_enable[2] = (q2 == 9)&(q1 == 9);
assign  OneHertz = (q3 == 9)&(q2 == 9)&(q1 == 9) ? 1 : 0;

bcdcount counter0 (clk, reset, c_enable[0], q1);
bcdcount counter1 (clk, reset, c_enable[1], q2);
bcdcount counter2 (clk, reset, c_enable[2], q3);

endmodule

第105题：4-digit decimal counter

module top_module 
(
    input           clk     ,
    input           reset   ,   // Synchronous active-high reset
    output [3:1]    ena     ,
    output [15:0]   q
);

assign  ena[1] = (q[3:0] == 9) ? 1 : 0;
assign  ena[2] = (q[3:0] == 9)&(q[7:4] == 9) ? 1 : 0;
assign  ena[3] = (q[3:0] == 9)&(q[7:4] == 9)&(q[11:8] == 9) ? 1 : 0;

decade_counters decade_counters_inst1
(
    .clk     (clk),
    .slowena (1'b1),
    .reset   (reset),
    .q       (q[3:0])
);

decade_counters decade_counters_inst2
(
    .clk     (clk),
    .slowena (ena[1]),
    .reset   (reset),
    .q       (q[7:4])
);

decade_counters decade_counters_inst3
(
    .clk     (clk),
    .slowena (ena[2]),
    .reset   (reset),
    .q       (q[11:8])
);

decade_counters decade_counters_inst4
(
    .clk     (clk),
    .slowena (ena[3]),
    .reset   (reset),
    .q       (q[15:12])
);

endmodule

module decade_counters  
(
    input           clk     ,
    input           slowena ,
    input           reset   ,
    output [3:0]    q
);

always@(posedge clk)
    if(reset)
        q <= 0;
    else if((q == 9)&&(slowena == 1'b1))
        q <= 0;
    else if(slowena)
        q <= q+1;

endmodule

第106题：12-hour clock

module top_module
(
    input                clk     ,
    input                reset   ,
    input                ena     ,
    output reg           pm      ,
    output reg  [7:0]    hh      ,
    output reg  [7:0]    mm      ,
    output reg  [7:0]    ss
); 

always@(posedge clk)
    if(reset)
        ss[3:0] <= 0;
    else if((ena == 1'b1)&&(ss[3:0] == 9))
        ss[3:0] <= 0;
    else if(ena)
        ss[3:0]<= ss[3:0]+1;

always@(posedge clk)
    if(reset)
        ss[7:4] <= 0;
    else if((ena == 1'b1)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        ss[7:4] <= 0;
    else if((ena == 1'b1)&&(ss[3:0] == 9))
        ss[7:4]<= ss[7:4]+1;

always@(posedge clk)
    if(reset)
        mm[3:0] <= 0;
    else if((ena == 1'b1)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        mm[3:0] <= 0;
    else if((ena == 1'b1)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        mm[3:0]<= mm[3:0]+1;

always@(posedge clk)
    if(reset)
        mm[7:4] <= 0;
    else if((ena == 1'b1)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        mm[7:4] <= 0;
    else if((ena == 1'b1)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        mm[7:4]<= mm[7:4]+1;

always@(posedge clk)
    if(reset)
        hh[3:0] <= 2;
    else if((ena == 1'b1)&&(hh[7:4] == 1)&&(hh[3:0] == 2)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        hh[3:0] <= 1;
    else if((ena == 1'b1)&&(hh[3:0] == 9)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        hh[3:0] <= 0;
    else if((ena == 1'b1)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        hh[3:0] <= hh[3:0]+1;

always@(posedge clk)
    if(reset)
        hh[7:4] <= 1;
    else if((ena == 1'b1)&&(hh[7:4] == 1)&&(hh[3:0] == 2)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        hh[7:4] <= 0;
    else if((ena == 1'b1)&&(hh[3:0] == 9)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        hh[7:4] <= 1;
        
always@(posedge clk)
    if(reset)
        pm <= 0;
    else if((ena == 1'b1)&&(hh[7:4] == 1)&&(hh[3:0] == 1)&&(mm[7:4]==5)&&(mm[3:0] == 9)&&(ss[7:4] == 5)&&(ss[3:0] == 9))
        pm <= ~pm;

endmodule

第107题：4-bit shift register

module top_module
(
    input               clk     ,
    input               areset  ,  // async active-high reset to zero
    input               load    ,
    input               ena     ,
    input       [3:0]   data    ,
    output reg  [3:0]   q
); 

always@(posedge clk or posedge areset)
    if(areset)
        q <= 4'b0;
    else if(load)
        q <= data;
    else if(ena)
        q <= q>>1;

endmodule

第108题：Left/right rotator

module top_module
(
    input               clk ,
    input               load,
    input       [1:0]   ena ,
    input       [99:0]  data,
    output reg  [99:0]  q
); 

always@(posedge clk)
    if(load)
        q <= data;
    else if(ena)
        begin
            case(ena)
                2'b00 : q <= q;
                2'b01 : q <= {q[0],q[99:1]};
                2'b10 : q <= {q[98:0],q[99]};
                2'b11 : q <= q;
                default :   q <= 100'bx;
            endcase
        end

endmodule

第109题：Left/right arithmetic shift by 1 or 8

module top_module
(
    input               clk     ,
    input               load    ,
    input               ena     ,
    input       [1:0]   amount  ,
    input       [63:0]  data    ,
    output reg  [63:0]  q
); 

always@(posedge clk)
    if(load)
        q <= data;
    else if(ena)
        begin
            case(amount)
                2'b00 : q <= q<<1;
                2'b01 : q <= q<<8;
                2'b10 : q <= {q[63],q[63:1]};
                2'b11 : q <= {{8{q[63]}},q[63:8]};
                default : q<= 64'bx;
            endcase
        end

endmodule

第110题：5-bit LFSR

module top_module
(
    input           clk     ,
    input           reset   ,    // Active-high synchronous reset to 5'h1
    output [4:0]    q
); 

always@(posedge clk)
    if(reset)
        q <= 5'b1;
    else
        q <= {0^q[0],q[4],q[3]^q[0],q[2],q[1]};

endmodule