牛客网verilog VL26 含有无关项的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0]tmp;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			match<=0;
			tmp<=9'd0;
		end
		else begin
			tmp[8:0]<={tmp[7:0],a};
		end
	end
	
	always@(posedge clk or negedge rst_n)begin
		if((tmp[8:6]==3'b011)&&(tmp[2:0]==3'b110))begin
			match<=1'b1;
		end
		else begin
			match<=1'b0;
		end
	end
endmodule	

没有想明白为什么不能9位一起检测