牛客网verilog VL5 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
always@(*)begin
	out<=0;
	validout<=0;
end
reg [15:0]memo;
always@(*)begin
	case(sel)
	0:validout<=0;
	1:validout<=1;
	2:validout<=1;
	3:validout<=1;
	endcase
	if(!sel)begin
		memo<=d;
	end
end

always@(*)begin
	case(sel)
	0:out<=0;
	1:out<=memo[3:0]+memo[7:4];
	2:out<=memo[3:0]+memo[11:8];
	3:out<=memo[3:0]+memo[15:12];
	endcase
end
//always@(*)和assing的区别，虽然都是组合逻辑
//*************code***********//
endmodule