牛客网verilog VL37 时钟分频（偶数）

注意复位时的初始值

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
reg [2:0] cnt;
reg [1:0] cnt1;
reg cnt2;
	always@(posedge clk_in or negedge rst)begin
		if(!rst)begin
			cnt <= 0;
			cnt1 <= 0;
			cnt2 <= 0;
		end
		else begin
			cnt = cnt + 1;
			cnt1 = cnt1 + 1;
			cnt2 = cnt2 +1;
		end
	end
	assign clk_out2 = (cnt2 < 1) ? 1 : 0;
	assign clk_out4 = (cnt1 < 2) ? 1 : 0;
	assign clk_out8 = (cnt < 4) ? 1 : 0;
endmodule