牛客网verilog VL36 状态机-重叠序列检测

注意看波形，是检测出结果后跳转至下一个状态的时候flag为1

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
	reg [2:0] state;
	always@(posedge clk or negedge rst)begin
		if(!rst)begin
			state <= 0;
			flag <= 0;
		end
		else begin
			case(state)
				3'd0:begin
					if(data == 1)begin
						state <= 3'd1;
						flag <= 0;
					end
					else begin
						state <= 3'd0;
						flag <= 0;
					end
				end
				3'd1:begin
					if(data == 0)begin
						state <= 3'd2;
						flag <= 0;
					end
					else begin
						state <= 3'd1;
						flag <= 0;
					end
				end
				3'd2:begin
					if(data == 1)begin
						state <= 3'd3;
						flag <= 0;
					end
					else begin
						state <= 3'd0;
						flag <= 0;
					end
				end
				3'd3:begin
					if(data == 1)begin
						state <= 3'd4;
						flag <= 0;
					end
					else begin
						state <= 3'd2;
						flag <= 0;
					end
				end
				3'd4:begin
					if(data == 1)begin
						state <= 3'd1;
						flag <= 1;
					end
					else begin
						state <=3'd2;
						flag <= 1;
					end
				end
				default:begin
					state <= 3'd0;
					flag <= 0;
				end
			endcase
		end
	end
endmodule