牛客网verilog VL27 不重叠序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	
	reg [2:0]cnt;
	reg [5:0]r_data;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			match<=0;
			not_match<=0;
			r_data<=0;
		end
		else begin
			r_data[5:0]<={r_data[4:0],data};
			if(cnt!=3'd5)begin
				cnt<=cnt+1;
			end
			else begin
				cnt<=0;
			end
		end
	end 
	always@(*)begin
		if((cnt[2:0] == 3'd5)&&(r_data[5:0]==8'b0111_00))begin
			match=1;
		end
		else if((cnt[2:0] == 3'd5)&&(r_data[5:0]!=8'b0111_00))begin
			not_match=1;
		end
		else begin
			match=0;
			not_match=0;
		end
	end
endmodule

//打怪升级