HDLBits刷题之2.2.1----Verilog Language----Vectors----Vectors

1.Vectors

Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.

题目意思是建立一个3位通道输入，然后输出一个整的，另外分别将每个通道输出。代码如下所示：

module top_module(
	input [2:0] vec, 
	output [2:0] outv,
	output o2,
	output o1,
	output o0
);
	//输出整的
	assign outv = vec;

    //分别输出
	assign o0 = vec[0];
	assign o1 = vec[1];
	assign o2 = vec[2];
	
endmodule