东北大学《逻辑与数字系统》数字显示秒表Verilog设计与测试

故故糕

于 2024-06-05 15:54:01 发布

阅读量875

点赞数 29

分类专栏：数电文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_74996590/article/details/139442086

版权

数电专栏收录该内容

3 篇文章 1 订阅

订阅专栏

实验3 数字显示秒表Verilog设计与测试

一、实验目的

掌握多位计数器的设计方法。
掌握各种进制的设计方法。
掌握数码管的动态扫描显示的设计方法。
掌握分频电路的设计方法。
掌握FPGA的层次化设计方法。

二、实验主要仪器设备

FPGA实验板。
FPGA实验板配套软件，ModelSim 10

三、设计任务与要求

1. 基本任务及要求

根据FPGA实验板功能，设计用数码管显示的秒表计数功能，具体要求如下：

按开始键KEY1后，进行秒加计时（从0开始）；按KEY2时，停止秒计时。

2. 扩展任务及要求

以KEY3作为控制键，切换正计时还是倒计时功能;
KEY3=0，用按键设置倒计时的初始值（初始值大于10秒）；按KEY1时，开始倒计时；按KEY2时，停止计时。KEY3=1，开始正计时。
倒计时的时间到，LED闪烁提示。

四、实验内容与步骤

1. 基本任务

(1)工作原理

模块定义与接口：模块watch定义了实验的主要功能，包括输入（时钟信号CLK、按键信号key1和key2、清零信号CLR）和输出（秒数Q、分钟数M以及数码管显示信号Q1和Q2）。

计时逻辑：使用一个分频器从主时钟CLK生成一个较慢的时钟信号CP，用于驱动秒计数。当按下开始键key1且停止键key2未被按下时，秒计数器Q开始计数。如果秒数达到59（即二进制8'b00111011），则分钟计数器M增加，并且秒计数器归零。当清零信号CLR有效时，所有计数器归零。

数码管显示逻辑：秒数Q被转换为BCD码（二进制编码的十进制数），以便在数码管上显示。通过BCD转换器模块bcd_converter将秒数Q转换为百位、十位和个位的BCD码。根据BCD码的值，通过查表方式在数码管上显示相应的数字。在本实验中，仅使用了十位和个位的数码管（Q1和Q2）。

分频器与时钟信号：分频器用于将主时钟信号CLK分频，生成一个较慢的时钟信号CP，用于控制秒表的计时速度。分频器通过计数到一个特定值（在本例中是28'd1，即2^28 - 1），然后翻转CP信号的状态来实现分频。

实验原理的关键在于利用FPGA的并行处理能力来实现计时和显示功能。通过精确控制时钟信号和按键输入，实验能够在数码管上实时显示经过的秒数，并允许用户通过按键开始和停止计时。此外，实验还展示了FPGA在数字逻辑设计和时序控制方面的灵活性。

(b) Verilog源程序


`timescale 1ns / 1ps

//

// Company:

// Engineer:

//

// Create Date: 2024/05/25 10:57:01

// Design Name:

// Module Name: BCD

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//



module BCD(

    input [7:0] binary,

    output reg [3:0] Hundreds,

    output reg [3:0] Tens,

    output reg [3:0] Ones

);

    integer i;

    always @(binary) begin

        // 初始化为0

        Hundreds = 4'd0;

        Tens = 4'd0;

        Ones = 4'd0;



        // 二进制转BCD算法

        for (i = 7; i >= 0; i = i - 1) begin

            if (Hundreds >= 5) Hundreds = Hundreds + 3;

            if (Tens >= 5) Tens = Tens + 3;

            if (Ones >= 5) Ones = Ones + 3;



            // 向左移位

            Hundreds = Hundreds << 1;

            Hundreds[0] = Tens[3];

            Tens = Tens << 1;

            Tens[0] = Ones[3];

            Ones = Ones << 1;

            Ones[0] = binary[i];

        end

    end

endmodule



module watch(



    input wire CLK, // 时钟信号

    input wire key1, // 按键1

    input wire key2, // 按键2

    input wire CLR, // 清零

    output reg [7:0] Q, // 输出秒数

    output reg [3:0] M, // 输出分钟数

    output reg [6:0] Q1, // 个位数码管

    output reg [6:0] Q2 // 十位数码管

);



    reg CP;

    reg [27:0] cnt;

    wire [3:0] BCD_Hundreds;

    wire [3:0] BCD_Tens;

    wire [3:0] BCD_Ones;



    // 实例化BCD转换模块

    BCD bcd_converter (

        .binary(Q),

        .Hundreds(BCD_Hundreds),

        .Tens(BCD_Tens),

        .Ones(BCD_Ones)

    );



    initial begin

        Q = 8'b00000000;

        M = 4'b0000;

        CP = 0;

        cnt = 28'd0;

    end



    always @(posedge CP or posedge CLR) begin

        if (CLR == 1) begin

            Q <= 8'b00000000;

            M <= 4'b0000; // 置零

        end

        else if (key1 == 1 && key2 == 0) begin

            if (Q == 8'b00111011) begin // 如果到59秒

                Q <= 8'b00000000;

                M <= M + 4'b0001; // 进位

            end

            else

                Q <= Q + 1;

        end

    end



    // 分频器

    always @(posedge CLK) begin

        if (cnt != 28'd1) // 3124999

            cnt <= cnt + 1'b1;

        else

            cnt <= 28'd0;



        if (cnt == 28'd0)

            CP <= ~CP; // 在分频器的每个周期开始时取反时钟信号



        // 打印调试信息

        $display("Time: %d, CLK: %b, CP: %b, cnt: %d, Q: %d, M: %d", $time, CLK, CP, cnt, Q, M);

    end



    // 数码管显示逻辑（共阴极）

    always @* begin

        case(BCD_Ones)

            4'b0000: Q1 = 7'b0111111; // 0

            4'b0001: Q1 = 7'b0000110; // 1

            4'b0010: Q1 = 7'b1011011; // 2

            4'b0011: Q1 = 7'b1001111; // 3

            4'b0100: Q1 = 7'b1100110; // 4

            4'b0101: Q1 = 7'b1101101; // 5

            4'b0110: Q1 = 7'b1111101; // 6

            4'b0111: Q1 = 7'b0000111; // 7

            4'b1000: Q1 = 7'b1111111; // 8

            4'b1001: Q1 = 7'b1101111; // 9

            default: Q1 = 7'b0000000; // 默认空白

        endcase



        case(BCD_Tens)

            4'b0000: Q2 = 7'b0111111; // 0

            4'b0001: Q2 = 7'b0000110; // 1

            4'b0010: Q2 = 7'b1011011; // 2

            4'b0011: Q2 = 7'b1001111; // 3

            4'b0100: Q2 = 7'b1100110; // 4

            4'b0101: Q2 = 7'b1101101; // 5

            4'b0110: Q2 = 7'b1111101; // 6

            4'b0111: Q2 = 7'b0000111; // 7

            4'b1000: Q2 = 7'b1111111; // 8

            4'b1001: Q2 = 7'b1101111; // 9

            default: Q2 = 7'b0000000; // 默认空白

        endcase

    end



endmodule

(d) ModelSim源程序


`timescale 1ns / 1ps



module watch_tb;



    // 信号声明

    reg CLK = 0; // 初始化时钟信号为逻辑低电平

    reg key1;

    reg key2;

    reg CLR;

    wire [7:0] Q;

    wire [3:0] M;

    wire [6:0] Q1;

    wire [6:0] Q2;



    // 实例化被测试的 watch 模块

    watch watch_inst (

        .CLK(CLK),

        .key1(key1),

        .key2(key2),

        .CLR(CLR),

        .Q(Q),

        .M(M),

        .Q1(Q1),

        .Q2(Q2)

    );



    // 时钟产生器

    always #1 CLK = ~CLK;



    // 模拟按键输入

    initial begin

        key1 = 0;

        key2 = 0;

        CLR = 0;



        // 等待一段时间，然后按下key1

        #10 key1 = 1;

        #800 key1 = 0; // 保持按键按下200ns时间

      

        // 等待一段时间，然后按下key2

        #40 key2 = 1;

        #20 key2 = 0; // 保持按键按下200ns时间

       

        // 等待一段时间，然后置零CLR

        #10 CLR = 1;

        #10 CLR = 0;



        // 仿真结束

        #1000 $finish;

    end



    // 打印调试信息

    always @(posedge CLK) begin

        $monitor("Time: %d, CLK: %b, key1: %b, key2: %b, CLR: %b, Q: %d, M: %d, Q1: %b, Q2: %b", $time, CLK, key1, key2, CLR, Q, M, Q1, Q2);

    end



endmodule

(d) ModelSim仿真结果

key1为高电平表示正计时开始key2为高电平表示暂停，CLR为高电平表示清零

Q代表的是秒（0-59s）,M代表的是分钟，Q1Q2分别是秒的个位和十位的数码管

分析如下：

1.当key1为高电平时，计数器开始计时，可见秒的Q在增加

2.当在 key1为高电平时，秒到59秒（3b）,会向分钟进位，此时分钟M由0变为1

3.当key2为高电平时暂停，可见秒和分钟不会变化

4.当CLR为高电平时分钟和秒都会被清零：

(e) 下载测试结果

管脚配置


#Clock

set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports CLK] ;#50MHz main clock in

set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS33} [get_ports clk_11M0592] ;#11.0592MHz clock for UART

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_11M0592_IBUF]



create_clock -period 20.000 -name clk_50M -waveform {0.000 10.000} [get_ports clk_50M]

create_clock -period 90.422 -name clk_11M0592 -waveform {0.000 45.211} [get_ports clk_11M0592]



#Touch Button

set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports touch_btn[0]] ;#BTN1

set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports touch_btn[1]] ;#BTN2

set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports touch_btn[2]] ;#BTN3

set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports touch_btn[3]] ;#BTN4

set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports clock_btn] ;#BTN5

set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports reset_btn] ;#BTN6



#required if touch button used as manual clock source

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock_btn_IBUF]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_btn_IBUF]



#CPLD GPIO 12-16

#set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {uart_wrn}]

#set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {uart_rdn}]

#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {uart_tbre}]

#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {uart_tsre}]

#set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {uart_dataready}]



#Ext serial

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN H18} [get_ports txd] ;#GPIO5

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN J20} [get_ports rxd] ;#GPIO6



#Digital Video

set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports video_clk]

set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS33} [get_ports {video_red[2]}]

set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS33} [get_ports {video_red[1]}]

set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports {video_red[0]}]

set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS33} [get_ports {video_green[2]}]

set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS33} [get_ports {video_green[1]}]

set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS33} [get_ports {video_green[0]}]

set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS33} [get_ports {video_blue[1]}]

set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS33} [get_ports {video_blue[0]}]

set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports video_hsync]

set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS33} [get_ports video_vsync]

set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS33} [get_ports video_de]



#LEDS

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports {Q[0]}]

set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {Q[1]}]

set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {Q[2]}]

set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {Q[3]}]

set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports {Q[4]}]

set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports {Q[5]}]

set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports {Q[6]}]

set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {Q[7]}]

set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports {leds[8]}]

set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports {M[0]}]

set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {M[1]}]

set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {M[2]}]

set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {M[3]}]

set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports {leds[13]}]

set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {leds[14]}]

set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {leds[15]}]



#DPY0

set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {dpy0[0]}]

set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {Q1[2]}]

set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports {Q1[3]}]

set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {Q1[4]}]

set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {Q1[1]}]

set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {Q1[0]}]

set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {Q1[5]}]

set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {Q1[6]}]



#DPY1

set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {dpy2[0]}]

set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports {Q2[2]}]

set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {Q2[3]}]

set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports {Q2[4]}]

set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {Q2[1]}]

set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {Q2[0]}]

set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {Q2[5]}]

set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {Q2[6]}]



#DIP_SW

set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {key1}]

set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {key2}]

set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {CLR}]

set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[3]}]

set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[4]}]

set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[5]}]

set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[6]}]

set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[7]}]

set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[8]}]

set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[9]}]

set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[10]}]

set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[11]}]

set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[12]}]

set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[13]}]

set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[14]}]

set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[15]}]

set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[16]}]

set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[17]}]

set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[18]}]

set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[19]}]

set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[20]}]

set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[21]}]

set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[22]}]

set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[23]}]

set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[24]}]

set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[25]}]

set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[26]}]

set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[27]}]

set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[28]}]

set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[29]}]

set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[30]}]

set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[31]}]



set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33}  [get_ports {flash_a[0]}]

set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS33} [get_ports {flash_a[1]}]

set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports {flash_a[2]}]

set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS33} [get_ports {flash_a[3]}]

set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports {flash_a[4]}]

set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports {flash_a[5]}]

set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports {flash_a[6]}]

set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS33} [get_ports {flash_a[7]}]

set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports {flash_a[8]}]

set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS33} [get_ports {flash_a[9]}]

set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {flash_a[10]}]

set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports {flash_a[11]}]

set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {flash_a[12]}]

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {flash_a[13]}]

set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS33} [get_ports {flash_a[14]}]

set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {flash_a[15]}]

set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {flash_a[16]}]

set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {flash_a[17]}]

set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports {flash_a[18]}]

set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {flash_a[19]}]

set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {flash_a[20]}]

set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {flash_a[21]}]

set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {flash_a[22]}]



set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {flash_d[0]}]

set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {flash_d[1]}]

set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports {flash_d[2]}]

set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {flash_d[3]}]

set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {flash_d[4]}]

set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {flash_d[5]}]

set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports {flash_d[6]}]

set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {flash_d[7]}]

set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {flash_d[8]}]

set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {flash_d[9]}]

set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {flash_d[10]}]

set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS33} [get_ports {flash_d[11]}]

set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {flash_d[12]}]

set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {flash_d[13]}]

set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {flash_d[14]}]

set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {flash_d[15]}]



set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33}  [get_ports flash_byte_n]

set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports flash_ce_n  ]

set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33}  [get_ports flash_oe_n  ]

set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports flash_rp_n  ]

set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports flash_vpen  ]

set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33}  [get_ports flash_we_n  ]



set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[0]}]

set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[1]}]

set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[2]}]

set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[3]}]

set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[4]}]

set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[5]}]

set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[6]}]

set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[7]}]

set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[8]}]

set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[9]}]

set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[10]}]

set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[11]}]

set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[12]}]

set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[13]}]

set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[14]}]

set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[15]}]

set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[16]}]

set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[17]}]

set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[18]}]

set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[19]}]

set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[1]}]

set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[0]}]

set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[3]}]

set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[2]}]

set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[0]}]

set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[1]}]

set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[2]}]

set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[3]}]

set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[4]}]

set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[5]}]

set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[6]}]

set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[7]}]

set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[8]}]

set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[9]}]

set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[10]}]

set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[11]}]

set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[12]}]

set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[13]}]

set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[14]}]

set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[15]}]

set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[16]}]

set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[17]}]

set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[18]}]

set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[19]}]

set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[20]}]

set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[21]}]

set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[22]}]

set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[23]}]

set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[24]}]

set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[25]}]

set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[26]}]

set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[27]}]

set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[28]}]

set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[29]}]

set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[30]}]

set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[31]}]

set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports base_ram_ce_n]

set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports base_ram_oe_n]

set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports base_ram_we_n]



set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[0]}]

set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[1]}]

set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[2]}]

set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[3]}]

set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[4]}]

set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[5]}]

set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[6]}]

set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[7]}]

set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[8]}]

set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[9]}]

set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[10]}]

set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[11]}]

set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[12]}]

set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[13]}]

set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[14]}]

set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[15]}]

set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[16]}]

set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[17]}]

set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[18]}]

set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[19]}]

set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[1]}]

set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[0]}]

set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[3]}]

set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[2]}]

set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[0]}]

set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[1]}]

set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[2]}]

set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[3]}]

set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[4]}]

set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[5]}]

set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[6]}]

set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[7]}]

set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[8]}]

set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[9]}]

set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[10]}]

set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[11]}]

set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[12]}]

set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[13]}]

set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[14]}]

set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[15]}]

set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[16]}]

set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[17]}]

set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[18]}]

set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[19]}]

set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[20]}]

set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[21]}]

set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[22]}]

set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[23]}]

set_property -dict {PACKAGE_PIN AD17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[24]}]

set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[25]}]

set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[26]}]

set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[27]}]

set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[28]}]

set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[29]}]

set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[30]}]

set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[31]}]

set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33} [get_ports ext_ram_ce_n]

set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports ext_ram_oe_n]

set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports ext_ram_we_n]



set_property CFGBVS VCCO [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

测试图

拨码开关1表示的是开始，2表示的是暂停，3表示的是

下图时暂停后的显示，D1-D4代表的是秒的二进制位，数码管显示的是15，所以，D1-D4代表的是15

拨码开关3拨上去代表的是清零，此时数码管显示的是0

2. 扩展任务

(1)工作原理

clk：50MHz的时钟输入，为整个系统提供时钟基准。

key3：功能切换键，用于在正计时和倒计时设置之间切换。

key1：在倒计时模式下，用于启动倒计时。

key2：用于停止所有计时功能。

num 和 numf：分别用于设置倒计时的秒数和分钟数。

duan1 和 duan2：数码管显示信号，分别显示时间的十位和个位。

fen：当前分钟数的显示。

light：灯光信号，用于倒计时结束时闪烁提示。

时钟分频与产生1Hz信号：于FPGA的时钟频率很高（如50MHz），需要通过分频来产生一个1Hz的时钟信号（clk_1hz），以便进行秒级计时。这是通过一个计数器实现的，每当计数器达到一定数值时，就切换clk_1hz的状态。

正计时功能：当key3为高电平时，系统进入正计时模式。在每个1Hz的时钟上升沿，秒数增加。当秒数达到60时，分钟数增加，并且秒数归零。分钟和秒的增加都是通过BCD码（二进制编码的十进制数）进行的，这样可以方便地在数码管上显示。

倒计时功能：当key3为低电平时，可以通过key1启动倒计时。倒计时的初始值由num和numf设置。在每个1Hz的时钟上升沿，倒计时秒数减少。当倒计时到达0时，灯光信号light会开始闪烁以提示用户。

数码管显示：使用BCD码将当前的秒数（或分钟数）转换为数码管可以显示的格式。十位和个位数分别通过duan1和duan2输出到数码管进行显示。

灯光闪烁提示：当倒计时结束时，ju标志被设置，触发灯光闪烁逻辑。灯光信号light会以一定的频率切换状态，从而实现闪烁效果。

本实验通过FPGA实现了正计时和倒计时的功能，并通过数码管显示时间和灯光闪烁进行提示。这充分展示了FPGA在时序控制和数字逻辑处理方面的能力。

(b) Verilog源程序


`timescale 1ns / 1ps



module second(

    clk, // 50MHz时钟输入

    duan1, // 数码管显示的十位数

    duan2, // 数码管显示的个位数

    key3, // key3=1 正计时开始，key3=0 设置倒计时数

    key2, // key2=1 所有计时结束

    key1, // key1=1 倒计时开始

    num, // 倒计时数设置（7位）

    numf, // 初始倒计时分钟数（8位）

    light, // 灯光信号

    fen // 当前分钟数显示

);

input key3; // 正计时控制信号

input key2; // 计时结束控制信号

input key1; // 倒计时控制信号

input [6:0] num; // 倒计时初始值（秒）

input [7:0] numf; // 倒计时初始值（分钟）

reg [6:0] num_st; // 保存设置的倒计时数

input clk; // 输入时钟信号

output reg [7:0] fen; // 分钟数显示

output reg light; // 灯光控制信号

output [7:0] duan1, duan2; // 数码管显示信号

reg [7:0] duan1, duan2; // 数码管显示寄存器

integer count; // 1Hz时钟计数器

integer count2; // 数码管扫描时钟计数器

integer countl; // 灯光闪烁计数器

reg clk_1hz; // 1Hz时钟信号

reg [3:0] ge; // 个位数的BCD码

reg [2:0] shi; // 十位数的BCD码

reg clk_scan; // 数码管扫描时钟信号

reg select; // 数码管选择信号

reg initialized; // 初始化标志，判断能否设置倒计时数

reg ju; // 灯光闪烁判断



// 初始块，初始化所有寄存器和变量

initial begin

    count = 0;

    count2 = 0;

    countl = 0;

    clk_1hz = 0;

    ge = 0;

    shi = 0;

    clk_scan = 0;

    select = 0;

    initialized = 0;

    ju = 0;

    duan1 = 8'b0011_1111;

    duan2 = 8'b0011_1111;

    light = 0;

    fen = 8'b0011_1111;

end



// 时钟控制块，用于产生1Hz的时钟信号以及控制灯光闪烁

always @(posedge clk) begin

    if((key1 == 1 || key3 == 1) && key2 == 0) begin

        if(count == 25) begin

            clk_1hz = ~clk_1hz; // 产生1Hz时钟信号

            count = 0;

        end else begin

            count = count + 1'b1;

        end

    end

    if(ju == 1) begin

        if(countl == 25) begin

            light = ~light; // 控制灯光闪烁

            countl = 0;

        end else begin

            countl = countl + 1'b1;

        end

    end

    if(ju == 0) begin

        light = 0; // 灯光熄灭

    end

end



// 秒表功能块，用于处理正计时和倒计时功能

always @(posedge clk_1hz) begin

    if(key3 == 0 && !initialized) begin

        {shi, ge} = num; // 初始化倒计时数

        fen = numf; // 初始化倒计时分钟数

        initialized = 1;

    end else if(key3 == 1) begin

        initialized = 0;

        ju = 0;

        if(ge == 4'b1001) begin

            ge = 4'b0000;

            if(shi == 3'b101) begin

                shi = 3'b000;

                if(fen[3:0] == 4'b1001) begin

                    fen[3:0] = 4'b0000;

                    if(fen[7:4] == 4'b0101) begin

                        fen[7:4] = 0;

                    end else begin

                        fen[7:4] = fen[7:4] + 1;

                    end

                end else begin

                    fen = fen + 1;

                end

            end else begin

                shi = shi + 1'b1;

            end

        end else begin

            ge = ge + 1'b1;

        end

    end else if(key1 == 1) begin

        if(ge == 4'b0000 && shi == 3'b000 && fen == 0) begin

            ge = 4'b0000;

            shi = 3'b000;

            fen = 0;

            ju = 1;

        end else if(ge == 4'b0000) begin

            ju = 0;

            ge = 4'b1001;

            if(shi == 3'b000) begin

                shi = 3'b101;

                if(fen[3:0] == 4'b0000) begin

                    fen[3:0] = 4'b1001;

                    fen[7:4] = fen[7:4] - 1;

                end else begin

                    fen[3:0] = fen[3:0] - 1;

                end

            end else begin

                shi = shi - 1'b1;

            end

        end else begin

            ge = ge - 1'b1;

            ju = 0;

        end

    end

end



// 数码管扫描时钟产生块

always @(posedge clk) begin

    if(count2 == 1) begin

        count2 = 0;

        clk_scan = ~clk_scan; // 产生数码管扫描时钟信号

    end else begin

        count2 = count2 + 1;

    end

end



// 数码管选择信号切换

always @(posedge clk_scan) begin

    select = select + 1'b1;

end

always @(ge or shi or select) begin

    if(select == 1'b1) begin

        case(ge)

            4'b0000: begin duan1 = 8'b0011_1111; end

            4'b0001: begin duan1 = 8'b0000_0110; end

            4'b0010: begin duan1 = 8'b0101_1011; end

            4'b0011: begin duan1 = 8'b0100_1111; end

            4'b0100: begin duan1 = 8'b0110_0110; end

            4'b0101: begin duan1 = 8'b0110_1101; end

            4'b0110: begin duan1 = 8'b0111_1101; end

            4'b0111: begin duan1 = 8'b0000_0111; end

            4'b1000: begin duan1 = 8'b0111_1111; end

            4'b1001: begin duan1 = 8'b0110_1111; end

            default: duan1 = 8'bx;

        endcase    

    end else begin

        case(shi)

            4'b0000: begin duan2 = 8'b0011_1111; end

            4'b0001: begin duan2 = 8'b0000_0110; end

            4'b0010: begin duan2 = 8'b0101_1011; end

            4'b0011: begin duan2 = 8'b0100_1111; end

            4'b0100: begin duan2 = 8'b0110_0110; end

            4'b0101: begin duan2 = 8'b0110_1101; end

            4'b0110: begin duan2 = 8'b0111_1101; end

            4'b0111: begin duan2 = 8'b0000_0111; end

            4'b1000: begin duan2 = 8'b0111_1111; end

            4'b1001: begin duan2 = 8'b0110_1111; end

            default: duan2 = 8'bx;

        endcase

    end

end



endmodule

(d) ModelSim源程序


`timescale 1ns / 1ps



module second_tb;



    reg clk;

    reg key3;

    reg key2;

    reg key1;

    reg [6:0] num;

    reg [7:0] numf;

    wire [7:0] duan1, duan2;

    wire light;

    wire [7:0] fen;



    // Instantiate the unit under test (UUT)

    second uut (

        .clk(clk),

        .key3(key3),

        .key2(key2),

        .key1(key1),

        .num(num),

        .numf(numf),

        .duan1(duan1),

        .duan2(duan2),

        .light(light),

        .fen(fen)

    );



    // Clock generation

    always #10 clk = ~clk; // Generate a 50 MHz clock



    initial begin

        // Initialize inputs

        clk = 0;

        key3 = 0;

        key2 = 0;

        key1 = 0;

        num = 7'd0;

        numf = 8'd0;



        // Wait for global reset to finish

        #100;



        // Test case 1: Set countdown number and start countdown

        num = 7'd10; // Set to 10 seconds

        numf = 8'd59; // Set to 59 minutes

        key3 = 1;

        #20 key3 = 0;



        // Test case 2: Start countdown

        key1 = 1;

        #2000000; // Wait for 20 seconds

        key1 = 0;



        // Test case 3: Pause countdown

        key1 = 1;

        #1000000; // Wait for 10 second

        key1 = 0;



        // Test case 4: Stop countdown

        key2 = 1;

        #20 key2 = 0;



        // Test case 5: Start normal counting

        key3 = 1;

        #2000000; // Wait for 2 seconds

        key3 = 0;



        // Test case 6: Stop counting

        key2 = 1;

        #20 key2 = 0;



        // Finish simulation

        #100;

        $finish;

    end



endmodule

(d) ModelSim仿真结果

Key3位低电平表示的是倒计时，为高电平时表示的时正计时 key1为0表示开始，

Key2为高电频表示的时暂停，num表示的是倒计时设置的初始值的秒numf表示的是倒计时设置的初始值的分钟，duan1表示的是秒的个位的数字所对应的数码管的二进制duan表示的是秒的十位的数字所对应的数码管的二进制

分析如下：

1. Key3为低电平表示是倒计时，key1为高电平表示是开始计时，此时分钟numf设置的是3b即59min ,秒设置3b即59s

2.当秒减到0时，分钟减一(fen{7:0}减1)

3.当key3切换到高电平时正计时

秒06对应的是数码管个位的的1,，5b代表的是数码管个位的1， 3f对应的数码管十位的0

(e) 下载测试结果

管脚配置

#Clock

set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports clk] ;#50MHz main clock in

set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS33} [get_ports clk_11M0592] ;#11.0592MHz clock for UART

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_11M0592_IBUF]



create_clock -period 20.000 -name clk_50M -waveform {0.000 10.000} [get_ports clk_50M]

create_clock -period 90.422 -name clk_11M0592 -waveform {0.000 45.211} [get_ports clk_11M0592]



#Touch Button

set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports touch_btn[0]] ;#BTN1

set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports touch_btn[1]] ;#BTN2

set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports touch_btn[2]] ;#BTN3

set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports touch_btn[3]] ;#BTN4

set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports clock_btn] ;#BTN5

set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports reset_btn] ;#BTN6



#required if touch button used as manual clock source

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock_btn_IBUF]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_btn_IBUF]



#CPLD GPIO 12-16

#set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {uart_wrn}]

#set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {uart_rdn}]

#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {uart_tbre}]

#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {uart_tsre}]

#set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {uart_dataready}]



#Ext serial

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN H18} [get_ports txd] ;#GPIO5

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN J20} [get_ports rxd] ;#GPIO6



#Digital Video

set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports video_clk]

set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS33} [get_ports {video_red[2]}]

set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS33} [get_ports {video_red[1]}]

set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports {video_red[0]}]

set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS33} [get_ports {video_green[2]}]

set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS33} [get_ports {video_green[1]}]

set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS33} [get_ports {video_green[0]}]

set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS33} [get_ports {video_blue[1]}]

set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS33} [get_ports {video_blue[0]}]

set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports video_hsync]

set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS33} [get_ports video_vsync]

set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS33} [get_ports video_de]



#LEDS

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports {light}]

set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {leds[1]}]

set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {leds[2]}]

set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {leds[3]}]

set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports {leds[4]}]

set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports {leds[5]}]

set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports {leds[6]}]

set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {leds[7]}]

set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports {fen[0]}]

set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports {fen[1]}]

set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {fen[2]}]

set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {fen[3]}]

set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {fen[4]}]

set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports {fen[5]}]

set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {fen[6]}]

set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {fen[7]}]



#DPY0

set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {duan1[7]}]

set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {duan1[2]}]

set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports {duan1[3]}]

set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {duan1[4]}]

set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {duan1[1]}]

set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {duan1[0]}]

set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {duan1[5]}]

set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {duan1[6]}]



#DPY1

set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {duan2[7]}]

set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports {duan2[2]}]

set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {duan2[3]}]

set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports {duan2[4]}]

set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {duan2[1]}]

set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {duan2[0]}]

set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {duan2[5]}]

set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {duan2[6]}]



#DIP_SW

set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {key3}]

set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {key2}]

set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {key1}]

set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {num[0]}]

set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {num[1]}]

set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {num[2]}]

set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {num[3]}]

set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {num[4]}]

set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {num[5]}]

set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {num[6]}]

set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {numf[0]}]

set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {numf[1]}]

set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {numf[2]}]

set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {numf[3]}]

set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {numf[4]}]

set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports {numf[5]}]

set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {numf[6]}]

set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {numf[7]}]

set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[18]}]

set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[19]}]

set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[20]}]

set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[21]}]

set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[22]}]

set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[23]}]

set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[24]}]

set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[25]}]

set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[26]}]

set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[27]}]

set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[28]}]

set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[29]}]

set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[30]}]

set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[31]}]



set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33}  [get_ports {flash_a[0]}]

set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS33} [get_ports {flash_a[1]}]

set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports {flash_a[2]}]

set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS33} [get_ports {flash_a[3]}]

set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports {flash_a[4]}]

set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports {flash_a[5]}]

set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports {flash_a[6]}]

set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS33} [get_ports {flash_a[7]}]

set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports {flash_a[8]}]

set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS33} [get_ports {flash_a[9]}]

set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {flash_a[10]}]

set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports {flash_a[11]}]

set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {flash_a[12]}]

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {flash_a[13]}]

set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS33} [get_ports {flash_a[14]}]

set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {flash_a[15]}]

set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {flash_a[16]}]

set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {flash_a[17]}]

set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports {flash_a[18]}]

set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {flash_a[19]}]

set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {flash_a[20]}]

set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {flash_a[21]}]

set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {flash_a[22]}]



set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {flash_d[0]}]

set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {flash_d[1]}]

set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports {flash_d[2]}]

set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {flash_d[3]}]

set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {flash_d[4]}]

set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {flash_d[5]}]

set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports {flash_d[6]}]

set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {flash_d[7]}]

set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {flash_d[8]}]

set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {flash_d[9]}]

set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {flash_d[10]}]

set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS33} [get_ports {flash_d[11]}]

set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {flash_d[12]}]

set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {flash_d[13]}]

set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {flash_d[14]}]

set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {flash_d[15]}]



set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33}  [get_ports flash_byte_n]

set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports flash_ce_n  ]

set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33}  [get_ports flash_oe_n  ]

set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports flash_rp_n  ]

set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports flash_vpen  ]

set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33}  [get_ports flash_we_n  ]



set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[0]}]

set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[1]}]

set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[2]}]

set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[3]}]

set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[4]}]

set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[5]}]

set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[6]}]

set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[7]}]

set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[8]}]

set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[9]}]

set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[10]}]

set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[11]}]

set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[12]}]

set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[13]}]

set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[14]}]

set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[15]}]

set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[16]}]

set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[17]}]

set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[18]}]

set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[19]}]

set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[1]}]

set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[0]}]

set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[3]}]

set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[2]}]

set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[0]}]

set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[1]}]

set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[2]}]

set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[3]}]

set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[4]}]

set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[5]}]

set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[6]}]

set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[7]}]

set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[8]}]

set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[9]}]

set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[10]}]

set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[11]}]

set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[12]}]

set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[13]}]

set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[14]}]

set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[15]}]

set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[16]}]

set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[17]}]

set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[18]}]

set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[19]}]

set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[20]}]

set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[21]}]

set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[22]}]

set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[23]}]

set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[24]}]

set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[25]}]

set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[26]}]

set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[27]}]

set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[28]}]

set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[29]}]

set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[30]}]

set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[31]}]

set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports base_ram_ce_n]

set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports base_ram_oe_n]

set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports base_ram_we_n]



set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[0]}]

set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[1]}]

set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[2]}]

set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[3]}]

set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[4]}]

set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[5]}]

set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[6]}]

set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[7]}]

set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[8]}]

set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[9]}]

set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[10]}]

set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[11]}]

set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[12]}]

set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[13]}]

set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[14]}]

set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[15]}]

set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[16]}]

set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[17]}]

set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[18]}]

set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[19]}]

set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[1]}]

set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[0]}]

set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[3]}]

set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[2]}]

set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[0]}]

set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[1]}]

set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[2]}]

set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[3]}]

set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[4]}]

set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[5]}]

set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[6]}]

set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[7]}]

set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[8]}]

set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[9]}]

set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[10]}]

set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[11]}]

set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[12]}]

set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[13]}]

set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[14]}]

set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[15]}]

set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[16]}]

set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[17]}]

set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[18]}]

set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[19]}]

set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[20]}]

set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[21]}]

set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[22]}]

set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[23]}]

set_property -dict {PACKAGE_PIN AD17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[24]}]

set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[25]}]

set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[26]}]

set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[27]}]

set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[28]}]

set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[29]}]

set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[30]}]

set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[31]}]

set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33} [get_ports ext_ram_ce_n]

set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports ext_ram_oe_n]

set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports ext_ram_we_n]



set_property CFGBVS VCCO [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

测试图