set up time and hold time 简单解释(文末附上进阶版解释,需要一定模拟基础)

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.
The setup time is the interval before the clock where the data must be held stable.
The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.
在这里插入图片描述

In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time period. If the data changes in this region, as shown the figure. The output may, follow the input, or many not follow the input, or may go to metastable state (where output cannot be recognized as either logic low or logic high, the entire process is known as metastability).
在这里插入图片描述
The above figure shows the restricted region (shaded region) for a flip-flop whose hold time is negative. The following diagram illustrates the restricted region of a D flip-flop. D is the input, Q is the output, and clock is the clock signal. If D changes in the restricted region, the flip-flop may not behave as expected, means Q is unpredictable.

在这里插入图片描述
To avoid setup time violations:
The combinational logic between the flip-flops should be optimized to get minimum delay.
Redesign the flip-flops to get lesser setup time.
Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
Play with clock skew (useful skews).
To avoid hold time violations:
By adding delays (using buffers).
One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).

  • may be expected one: which means output is not sure, it may be the one you expect. You can also say “may not be expected one”. “may” implies uncertainty. Thanks for the readers for their comments.

进阶版解释:https://www.edn.com/understanding-the-basics-of-setup-and-hold-time/?utm_referrer=https%3A%2F%2Fwww.google.com%2F

  • 1
    点赞
  • 0
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值