Verilog 循环移位操作
循环左移
// shift left
reg [5:0] sel;
always@(posedge sys_clk or negedge sys_rst_n)
if(!sys_rst_n)
sel <= 6'b000001;
else if(*****判断条件******)
sel <= {sel[4:0],sel[5]};
else
sel <= sel;
//shift right
always@(posedge sys_clk or negedge sys_rst_n)
if(!sys_rst_n)
sel <= 6'b000001;
else if(*****判断条件******)
sel <= {sel[0],sel[5:1]};
else
sel <= sel;