Lfsr32答案

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
always @(posedge clk) begin
    if(reset)begin
        q <= 32'h1;
    end 
    else begin
        q[31]<=1'b0^q[0];
        q[0]<=q[0]^q[1];
        q[1]<=q[0]^q[2];
        q[21]<=q[0]^q[22];
        q[30:22]<=q[31:23];
        q[20:2]<=q[21:3];
    end
        
end
endmodule
 

lfsr32 — Compile and simulate

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