module top_module (
input clk,
input a,
output [3:0] q );
always@(posedge clk)begin
if (a==1'b1)
q<=4'b0100;
else if(q==4'd6)
q<=1'b0;
else
q<=q+1'b1;
end
endmodule
Sim/circuit9
最新推荐文章于 2024-09-27 21:53:49 发布