Exams/2014 q4b答案

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF m1(KEY[3],KEY[1],SW[3],KEY[2],KEY[0],LEDR[3]);
    MUXDFF m2(LEDR[3],KEY[1],SW[2],KEY[2],KEY[0],LEDR[2]);
    MUXDFF m3(LEDR[2],KEY[1],SW[1],KEY[2],KEY[0],LEDR[1]);
    MUXDFF m4(LEDR[1],KEY[1],SW[0],KEY[2],KEY[0],LEDR[0]);

endmodule

module MUXDFF (input w,
input e,
input r,
input l,
input clk,
output q);
    wire c,d;
assign c=e?w:q;
    assign d=l?r:c;
    always@(posedge clk)begin
    q<=d;
    end
endmodule