module top_module (
input clock,
input a,
output p,
output q );
assign p = clock ? a : p;
always@(negedge clock)begin
q=a;
end
endmodule
Sim/circuit8
于 2023-10-19 09:08:40 首次发布
module top_module (
input clock,
input a,
output p,
output q );
assign p = clock ? a : p;
always@(negedge clock)begin
q=a;
end
endmodule