module top_module (
input clk,
input a,
output q );
always@(posedge clk)begin
q=~a;
end
endmodule
Sim/circuit7
最新推荐文章于 2024-10-17 16:08:47 发布
module top_module (
input clk,
input a,
output q );
always@(posedge clk)begin
q=~a;
end
endmodule