这里把时钟调快了一点,方便进行验证,如果要恢复正常,
请修改秒脉冲发生器部分
`timescale 1ns / 1ps
//16进制
module second(
input wire clk,
output reg sec);
reg [27:0]q1;
always @(posedge clk)
begin
if(q1==500000)
begin
q1<=0;
sec<=~sec;
end
else
q1<=q1+1;
end
endmodule
module cnt24(
input wire clk,//秒脉冲信号
input clk2,//标准时钟信号
input clear,
input stop,
output reg [3:0] cnt60_L,
output reg [3:0] cnt60_H,
output reg [3:0] cnt25_mL,
output reg [3:0] cnt25_mH
//output reg carry
);
initial begin
cnt60_L=0;
cnt60_H=0;
cnt25_mL=5;
cnt25_mH=2;
end
//状态编码
parameter
[2:0]work25=3'b000;
parameter
[2:0]pause25=3'b001;
parameter
[2:0]reset25=3'b010;
parameter
[2:0]work5=3'b011;
parameter
[2:0]pause5=3'b100;
parameter
[2:0]reset5=3'b101;
reg [2:0]cstate;
reg [2:0]nstate;
reg [2:0]en;
reg carry25=0,carry5=0;
//状态转移
always @(posedge clk2 ) //clk2 标准时钟信号
cstate<=nstate;
//次态判断
always @*
//if(jinwei)
case(cstate)
work25:
begin
if(stop==1)
nstate=pause25;
else if(carry25==1)
nstate=work5;
else
nstate=work25;
end
work5:
begin
if(stop==1)
nstate=pause5;
else if(carry5==1)
nstate=work25;
else
nstate=work5;
end
pause25:
begin
if(clear==1)
nstate=reset5;
else if(stop==1)
nstate