二十四进制 (BCD码)加法计数器 并用数码管显示
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/09 19:37:50
// Design Name:
// Module Name: cnt24
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module second(
input wire clk,
output reg sec);
reg [27:0]q1;
always @(posedge clk)
begin
if(q1==50000000)
begin
q1<=0;
sec<=~sec;
end
else
q1<=q1+1;
end
endmodule
module cnt24(
input wire clk,
output reg [3:0] cnt60_L,
output reg [3:0] cnt60_H,
output reg carry
);
initial begin
cnt60_L=2;
cnt60_H=2;
end