状态机学习

状态机学习

`timescale 1ns / 1ps

//本代码是状态机 在三个状态来回切换
//三个状态：IDLE 0 1,  S 1 0, S2 0 0;
module state_1(
input key1,
input key2,
input clk,
input rst,
output reg cnt_en,
output reg load
//output reg [1:0]cstate,
//output reg [1:0]nstate
    );
    //状态编码
parameter
	[1:0]s1=2'b00;
parameter
	[1:0]s2=2'b10;
parameter
	[1:0]IDLE=2'b01;
reg [1:0]cstate;
reg [1:0]nstate;
/*
reg [26:0]counter;
wire clk2Hz;
//counter 分频计数器
parameter CNT=50000000;
initial counter=0;
always @(posedge clk or posedge rst)

    if(rst)
        counter<=0;
    else if (counter==CNT-1)
        counter<=0;
    else counter<=counter+1;
    assign clk2Hz=(counter==CNT-1)?1:0;
   */
    
    
//状态转移
always @(posedge clk or posedge rst)
	if(rst)
		cstate<=IDLE;
	else
		cstate<=nstate;
	
//次态判断
always @*
    //if(clk2Hz)
        case(cstate)
            IDLE:
            begin
            if(key1==1)
            nstate=s1;
            else
            nstate=IDLE;
            end
            //nstate<=key1&s1|(~key1)&IDLE;
            s1://nstate<=key1&s2|(~key1)&s1;
            begin
            if(key1==1)nstate=s2;
            else nstate=s1;
            end
            s2://nstate<=key1&s1|key2&IDLE;
            begin
            if(key2==1)
            nstate=IDLE;
       
            else if(key1==1)
            nstate=s1;
            else
            nstate=s2;
           end
            default: nstate=IDLE;
        endcase
   // else
     //   nstate=cstate;

     
     
//次态输出
always @(posedge clk )//or posedge rst)
begin
    //else
        case(cstate)
            IDLE:begin cnt_en<=0;load<=1;end
            s1:begin cnt_en<=1;load<=0;end
            s2:begin cnt_en<=0;load<=0;end
            default:begin cnt_en<=0;load<=1;end
        endcase
 end
endmodule


module edgecheck(
input key1,key2,
input clk,rst,
output Yup1,Yup2
);
reg a1,b1;
always @(posedge clk,posedge rst)
if(rst)begin
	a1<=0;
	b1<=0;
end
else begin
	a1<=key1;
	b1<=a1;
end
assign Yup1=a1&(~b1);
reg a2,b2;
always @(posedge clk,posedge rst)
if(rst)begin
	a2<=0;
	b2<=0;
end
else begin
	a2<=key2;
	b2<=a2;
end
assign Yup2=a2&(~b2);
//assign Ydown=(~a)&b;
//assign Yan=~a;
//assign Ybn=~b;

endmodule



module  main(
input clk,
input rst,
input key1,
input key2,
output wire cnt_en,
output wire load
//output wire [1:0]nstate,
//output wire [1:0]cstate
);
wire Yup1,Yup2;
state_1 zhuo1(
.key1(Yup1),
.key2(Yup2),
.clk(clk),
.rst(rst),
.cnt_en(cnt_en),
.load(load)
//.nstate(nstate),
//.cstate(cstate)
);
edgecheck zhuo2(
.key1(key1),
.key2(key2),
.clk(clk),
.rst(rst),
.Yup1(Yup1),
.Yup2(Yup2)
);
endmodule

此处代码我编的感觉不是很顺畅，用标准模板反而达不到效果，我把一些多余的删除后反而成功了。
三个状态的相互转换。

备注：本代码由西安交通大学电气工程及其自动化专业教学使用，如有侵权，联系作者删除。 本代码为西安交通大学学生备忘而用。
如果有共同爱好者，可以一起学习
qq：2685783428

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