`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/11 08:15:03
// Design Name:
// Module Name: tomato
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
//16进制
module second(
input wire clk,
output reg sec);
reg [27:0]q1;
always @(posedge clk)
begin
if(q1==5000000)
begin
q1<=0;
sec<=~sec;
end
else
q1<=q1+1;
end
endmodule
module cnt24(
input wire clk,
output reg [3:0] cnt60_L,
output reg [3:0] cnt60_H,
output reg [3:0] cnt25_mL,
output reg [3:0] cnt25_mH,
output reg carry
);
initial begin
cnt60_L=9;
cnt60_H=5;
cnt25_mL=4;
cnt25_mH=2;
end
always @(posedge clk)
begin
carry<=0;
cnt60_L<=cnt60_L-1;
if(cnt60_L
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最新推荐文章于 2024-06-13 17:10:44 发布