`timescale 1ns / 1ps
module second(
input wire clk,
output reg sec);
reg [27:0]q1;
always @(posedge clk)
begin
if(q1==50000000)
begin
q1<=0;
sec<=~sec;
end
else
q1<=q1+1;
end
endmodule
module cnt24(
input wire clk,
output reg [3:0] cnt60_L,
output reg [3:0] cnt60_H,
output reg carry
);
initial begin
cnt60_L=9;
cnt60_H=5;
end
always @(posedge clk)
begin
carry<=0;
cnt60_L<=cnt60_L-1;
if(cnt60_L==0)
begin
cnt60_L<=9
60进制BCD 减法计数器 数码管显示 vivado
最新推荐文章于 2023-06-07 20:28:45 发布